mio_boot_reg_cfg 924 arch/mips/cavium-octeon/octeon-platform.c union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; mio_boot_reg_cfg 951 arch/mips/cavium-octeon/octeon-platform.c mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); mio_boot_reg_cfg 952 arch/mips/cavium-octeon/octeon-platform.c region_base = mio_boot_reg_cfg.s.base << 16; mio_boot_reg_cfg 953 arch/mips/cavium-octeon/octeon-platform.c region_size = (mio_boot_reg_cfg.s.size + 1) << 16; mio_boot_reg_cfg 954 arch/mips/cavium-octeon/octeon-platform.c if (mio_boot_reg_cfg.s.en && base_ptr >= region_base mio_boot_reg_cfg 956 arch/mips/cavium-octeon/octeon-platform.c is_16bit = mio_boot_reg_cfg.s.width; mio_boot_reg_cfg 973 arch/mips/cavium-octeon/octeon-platform.c mio_boot_reg_cfg.u64 = mio_boot_reg_cfg 975 arch/mips/cavium-octeon/octeon-platform.c region1_base = mio_boot_reg_cfg.s.base << 16; mio_boot_reg_cfg 976 arch/mips/cavium-octeon/octeon-platform.c region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; mio_boot_reg_cfg 977 arch/mips/cavium-octeon/octeon-platform.c if (!mio_boot_reg_cfg.s.en) mio_boot_reg_cfg 1028 arch/mips/cavium-octeon/octeon-platform.c union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; mio_boot_reg_cfg 1041 arch/mips/cavium-octeon/octeon-platform.c mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); mio_boot_reg_cfg 1042 arch/mips/cavium-octeon/octeon-platform.c region_base = mio_boot_reg_cfg.s.base << 16; mio_boot_reg_cfg 1043 arch/mips/cavium-octeon/octeon-platform.c region_size = (mio_boot_reg_cfg.s.size + 1) << 16; mio_boot_reg_cfg 1044 arch/mips/cavium-octeon/octeon-platform.c if (mio_boot_reg_cfg.s.en && base_ptr >= region_base