min_sclk         2210 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	u32 min_sclk = 10000; /* ??? */
min_sclk         2229 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	sclk = min_sclk;
min_sclk         2395 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 min_sclk;
min_sclk         2435 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			min_sclk = max_sclk;
min_sclk         2437 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			min_sclk = prev_sclk;
min_sclk         2439 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
min_sclk         2441 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (min_sclk < state->performance_levels[0].sclk)
min_sclk         2442 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			min_sclk = state->performance_levels[0].sclk;
min_sclk         2444 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (min_sclk == 0)
min_sclk         2468 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
min_sclk          571 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
min_sclk          579 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (min_sclk < data->gfx_min_freq_limit)
min_sclk          580 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		min_sclk = data->gfx_min_freq_limit;
min_sclk          582 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	min_sclk /= 100; /* transfer 10KHz to MHz */
min_sclk          618 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						min_sclk);
min_sclk          621 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						min_sclk);
min_sclk          661 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						min_sclk);
min_sclk          712 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->default_compute_power_profile.min_sclk =
min_sclk         2477 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		uint32_t min_sclk, uint32_t min_mclk)
min_sclk         2485 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
min_sclk         2145 drivers/gpu/drm/radeon/kv_dpm.c 	u32 min_sclk = 10000; /* ??? */
min_sclk         2164 drivers/gpu/drm/radeon/kv_dpm.c 	sclk = min_sclk;
min_sclk         2460 drivers/gpu/drm/radeon/ni_dpm.c 	u32 min_sclk;
min_sclk         2511 drivers/gpu/drm/radeon/ni_dpm.c 			min_sclk = max_sclk;
min_sclk         2513 drivers/gpu/drm/radeon/ni_dpm.c 			min_sclk = prev_sclk;
min_sclk         2515 drivers/gpu/drm/radeon/ni_dpm.c 			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
min_sclk         2517 drivers/gpu/drm/radeon/ni_dpm.c 		if (min_sclk < state->performance_levels[0].sclk)
min_sclk         2518 drivers/gpu/drm/radeon/ni_dpm.c 			min_sclk = state->performance_levels[0].sclk;
min_sclk         2520 drivers/gpu/drm/radeon/ni_dpm.c 		if (min_sclk == 0)
min_sclk         2524 drivers/gpu/drm/radeon/ni_dpm.c 			(u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
min_sclk         2298 drivers/gpu/drm/radeon/si_dpm.c 	u32 min_sclk;
min_sclk         2338 drivers/gpu/drm/radeon/si_dpm.c 			min_sclk = max_sclk;
min_sclk         2340 drivers/gpu/drm/radeon/si_dpm.c 			min_sclk = prev_sclk;
min_sclk         2342 drivers/gpu/drm/radeon/si_dpm.c 			min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
min_sclk         2345 drivers/gpu/drm/radeon/si_dpm.c 		if (min_sclk < state->performance_levels[0].sclk)
min_sclk         2346 drivers/gpu/drm/radeon/si_dpm.c 			min_sclk = state->performance_levels[0].sclk;
min_sclk         2348 drivers/gpu/drm/radeon/si_dpm.c 		if (min_sclk == 0)
min_sclk         2372 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
min_sclk         1047 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
min_sclk         1094 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
min_sclk         1095 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
min_sclk         1115 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].sclk < min_sclk)
min_sclk         1117 drivers/gpu/drm/radeon/sumo_dpm.c 				sumo_get_valid_engine_clock(rdev, min_sclk);
min_sclk         1675 drivers/gpu/drm/radeon/sumo_dpm.c 		pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
min_sclk           83 drivers/gpu/drm/radeon/sumo_dpm.h 	u32 min_sclk;
min_sclk         1404 drivers/gpu/drm/radeon/trinity_dpm.c 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
min_sclk         1543 drivers/gpu/drm/radeon/trinity_dpm.c 	u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
min_sclk         1544 drivers/gpu/drm/radeon/trinity_dpm.c 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
min_sclk         1567 drivers/gpu/drm/radeon/trinity_dpm.c 		if (ps->levels[i].sclk < min_sclk)
min_sclk         1569 drivers/gpu/drm/radeon/trinity_dpm.c 				trinity_get_valid_engine_clock(rdev, min_sclk);
min_sclk         1867 drivers/gpu/drm/radeon/trinity_dpm.c 		pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);
min_sclk           79 drivers/gpu/drm/radeon/trinity_dpm.h 	u32 min_sclk;