min_ref_div       606 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		ppll->min_ref_div = 2;
min_ref_div       636 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		spll->min_ref_div = 2;
min_ref_div       668 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 		mpll->min_ref_div = 2;
min_ref_div       389 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 		spll->min_ref_div = 2;
min_ref_div       412 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 		mpll->min_ref_div = 2;
min_ref_div       208 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 	uint32_t min_ref_div;
min_ref_div       144 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c 		ref_div_min = pll->min_ref_div;
min_ref_div       303 drivers/gpu/drm/radeon/radeon_clocks.c 	dcpll->min_ref_div = 2;
min_ref_div       309 drivers/gpu/drm/radeon/radeon_clocks.c 	p1pll->min_ref_div = 2;
min_ref_div       315 drivers/gpu/drm/radeon/radeon_clocks.c 	p2pll->min_ref_div = 2;
min_ref_div       324 drivers/gpu/drm/radeon/radeon_clocks.c 	spll->min_ref_div = 2;
min_ref_div       333 drivers/gpu/drm/radeon/radeon_clocks.c 	mpll->min_ref_div = 2;
min_ref_div       985 drivers/gpu/drm/radeon/radeon_display.c 		ref_div_min = pll->min_ref_div;
min_ref_div      1116 drivers/gpu/drm/radeon/radeon_display.c 	uint32_t min_ref_div = pll->min_ref_div;
min_ref_div      1133 drivers/gpu/drm/radeon/radeon_display.c 	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
min_ref_div      1148 drivers/gpu/drm/radeon/radeon_display.c 		min_ref_div = max_ref_div = pll->reference_div;
min_ref_div      1150 drivers/gpu/drm/radeon/radeon_display.c 		while (min_ref_div < max_ref_div-1) {
min_ref_div      1151 drivers/gpu/drm/radeon/radeon_display.c 			uint32_t mid = (min_ref_div + max_ref_div) / 2;
min_ref_div      1156 drivers/gpu/drm/radeon/radeon_display.c 				min_ref_div = mid;
min_ref_div      1189 drivers/gpu/drm/radeon/radeon_display.c 		for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
min_ref_div       183 drivers/gpu/drm/radeon/radeon_mode.h 	uint32_t min_ref_div;