min_post_divider  255 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		uint32_t min_post_divider,
min_post_divider  272 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			post_divider >= min_post_divider;
min_post_divider  297 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	uint32_t min_post_divider;
min_post_divider  310 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		min_post_divider = pll_settings->pix_clk_post_divider;
min_post_divider  313 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
min_post_divider  314 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
min_post_divider  316 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			min_post_divider = calc_pll_cs->min_vco_khz * 10 /
min_post_divider  318 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			if ((min_post_divider *
min_post_divider  321 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 				min_post_divider++;
min_post_divider  363 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (min_post_divider > max_post_divider) {
min_post_divider  385 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			min_post_divider,