min_dst_y_next_start 589 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); min_dst_y_next_start 869 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); min_dst_y_next_start 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, min_dst_y_next_start 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start, min_dst_y_next_start 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); min_dst_y_next_start 1067 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); min_dst_y_next_start 932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start min_dst_y_next_start 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); min_dst_y_next_start 950 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->min_dst_y_next_start); min_dst_y_next_start 932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start min_dst_y_next_start 934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); min_dst_y_next_start 950 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->min_dst_y_next_start); min_dst_y_next_start 979 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); min_dst_y_next_start 980 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); min_dst_y_next_start 1001 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->min_dst_y_next_start); min_dst_y_next_start 411 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int min_dst_y_next_start; min_dst_y_next_start 206 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.min_dst_y_next_start); min_dst_y_next_start 1157 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start min_dst_y_next_start 1159 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); min_dst_y_next_start 1171 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->min_dst_y_next_start);