min_dispclk_using_single_dpp 440 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); min_dispclk_using_single_dpp 448 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); min_dispclk_using_single_dpp 451 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { min_dispclk_using_single_dpp 453 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); min_dispclk_using_single_dpp 471 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); min_dispclk_using_single_dpp 474 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0); min_dispclk_using_single_dpp 479 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp); min_dispclk_using_single_dpp 480 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->min_dispclk_using_single_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) { min_dispclk_using_single_dpp 308 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h float min_dispclk_using_single_dpp;