min_clocks       3605 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct PP_Clocks min_clocks = {0};
min_clocks       3622 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
min_clocks       3623 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
min_clocks       3920 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct PP_Clocks min_clocks = {0};
min_clocks       3931 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
min_clocks       3932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
min_clocks       3933 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
min_clocks       3936 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
min_clocks       3946 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					min_clocks.dcefClockInSR / 100);
min_clocks       3954 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (min_clocks.memoryClock != 0) {
min_clocks       3955 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
min_clocks       1476 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct PP_Clocks min_clocks = {0};
min_clocks       1486 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
min_clocks       1487 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
min_clocks       1488 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
min_clocks       1492 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
min_clocks       1498 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					min_clocks.dcefClockInSR /100),
min_clocks       2296 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct PP_Clocks min_clocks = {0};
min_clocks       2300 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
min_clocks       2301 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
min_clocks       2302 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
min_clocks       2306 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
min_clocks       2311 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					min_clocks.dcefClockInSR / 100)) == 0,
min_clocks       2320 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
min_clocks       1255 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	struct smu_clocks min_clocks = {0};
min_clocks       1259 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
min_clocks       1260 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
min_clocks       1261 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
min_clocks       1265 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
min_clocks       1270 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 								  min_clocks.dcef_clock_in_sr/100);
min_clocks       1282 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
min_clocks       2255 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	struct smu_clocks min_clocks = {0};
min_clocks       2259 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
min_clocks       2260 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
min_clocks       2261 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
min_clocks       2265 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
min_clocks       2270 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 								  min_clocks.dcef_clock_in_sr/100);
min_clocks       2282 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;