min_chunk_size 557 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, min_chunk_size 566 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 1028 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, min_chunk_size 1038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, min_chunk_size 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, min_chunk_size 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, min_chunk_size 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 1226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, min_chunk_size 1236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 131 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, min_chunk_size 140 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, min_chunk_size 175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_chunk_size = 0; min_chunk_size 177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; min_chunk_size 175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_chunk_size = 0; min_chunk_size 177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; min_chunk_size 153 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_chunk_size = 0; min_chunk_size 155 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; min_chunk_size 485 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int min_chunk_size; min_chunk_size 164 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs.min_chunk_size); min_chunk_size 217 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_chunk_size = 0; min_chunk_size 219 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; min_chunk_size 7653 drivers/scsi/smartpqi/smartpqi_init.c u32 min_chunk_size; min_chunk_size 7658 drivers/scsi/smartpqi/smartpqi_init.c min_chunk_size = total_size / PQI_OFA_MAX_SG_DESCRIPTORS; min_chunk_size 7660 drivers/scsi/smartpqi/smartpqi_init.c for (chunk_sz = total_size; chunk_sz >= min_chunk_size; chunk_sz /= 2)