min_bpp           286 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const uint32_t min_bpp,
min_bpp           305 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	range->min_kbps = dsc_div_by_10_round_up(min_bpp * timing->pix_clk_100hz);
min_bpp           306 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	range->min_target_bpp_x16 = min_bpp * 16;
min_bpp           806 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		const uint32_t min_bpp,
min_bpp           829 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
min_bpp          1903 drivers/gpu/drm/i915/display/intel_dp.c 		limits->min_bpp = limits->max_bpp = bpp;
min_bpp          1952 drivers/gpu/drm/i915/display/intel_dp.c 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
min_bpp          2124 drivers/gpu/drm/i915/display/intel_dp.c 	limits.min_bpp = intel_dp_min_bpp(pipe_config);
min_bpp            29 drivers/gpu/drm/i915/display/intel_dp.h 	int min_bpp, max_bpp;
min_bpp            60 drivers/gpu/drm/i915/display/intel_dp_mst.c 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
min_bpp           130 drivers/gpu/drm/i915/display/intel_dp_mst.c 	limits.min_bpp = intel_dp_min_bpp(pipe_config);