mg_refclkin_ctl  12816 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
mg_refclkin_ctl  2675 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
mg_refclkin_ctl  3061 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));
mg_refclkin_ctl  3062 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
mg_refclkin_ctl  3203 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	val |= hw_state->mg_refclkin_ctl;
mg_refclkin_ctl  3422 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->mg_refclkin_ctl,
mg_refclkin_ctl   201 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 mg_refclkin_ctl;
mg_refclkin_ctl  2848 drivers/gpu/drm/i915/i915_debugfs.c 			   pll->state.hw_state.mg_refclkin_ctl);