mg_pll_frac_lock 12822 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
mg_pll_frac_lock 2819 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
mg_pll_frac_lock 2825 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
mg_pll_frac_lock 3080 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));
mg_pll_frac_lock 3222 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);
mg_pll_frac_lock 3428 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->mg_pll_frac_lock,
mg_pll_frac_lock  207 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 mg_pll_frac_lock;
mg_pll_frac_lock 2860 drivers/gpu/drm/i915/i915_debugfs.c 			   pll->state.hw_state.mg_pll_frac_lock);