mg_pll_div1      1416 drivers/gpu/drm/i915/display/intel_ddi.c 	m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
mg_pll_div1      12820 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
mg_pll_div1      2808 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
mg_pll_div1      3078 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
mg_pll_div1      3220 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
mg_pll_div1      3426 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->mg_pll_div1,
mg_pll_div1       205 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 mg_pll_div1;
mg_pll_div1      2856 drivers/gpu/drm/i915/i915_debugfs.c 			   pll->state.hw_state.mg_pll_div1);