mg_pll_div0      1417 drivers/gpu/drm/i915/display/intel_ddi.c 	m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
mg_pll_div0      1418 drivers/gpu/drm/i915/display/intel_ddi.c 	m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
mg_pll_div0      1419 drivers/gpu/drm/i915/display/intel_ddi.c 		(pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
mg_pll_div0      12819 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
mg_pll_div0      2804 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
mg_pll_div0      3077 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
mg_pll_div0      3219 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
mg_pll_div0      3425 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->mg_pll_div0,
mg_pll_div0       204 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 mg_pll_div0;
mg_pll_div0      2854 drivers/gpu/drm/i915/i915_debugfs.c 			   pll->state.hw_state.mg_pll_div0);