mfc_sr1_RW        477 arch/powerpc/include/asm/spu.h 	u64 mfc_sr1_RW;						/* 0x000 */
mfc_sr1_RW        123 arch/powerpc/include/asm/spu_csa.h 	u64 mfc_sr1_RW;
mfc_sr1_RW        103 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_sr1_RW, sr1);
mfc_sr1_RW        108 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_sr1_RW);
mfc_sr1_RW        301 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
mfc_sr1_RW        302 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
mfc_sr1_RW        312 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
mfc_sr1_RW        313 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
mfc_sr1_RW        217 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
mfc_sr1_RW       1694 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
mfc_sr1_RW       2149 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
mfc_sr1_RW        544 arch/powerpc/platforms/ps3/spu.c 		offsetof(struct spu_priv1, mfc_sr1_RW),