mfc_control_RW    411 arch/powerpc/include/asm/spu.h 	u64 mfc_control_RW;					/* 0x3000 */
mfc_control_RW    194 arch/powerpc/include/asm/spu_csa.h 	u64 mfc_control_RW;
mfc_control_RW    128 arch/powerpc/platforms/cell/spu_base.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
mfc_control_RW    368 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
mfc_control_RW   1816 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
mfc_control_RW   1818 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
mfc_control_RW   1826 arch/powerpc/platforms/cell/spufs/file.c 	if (ctx->csa.priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING)
mfc_control_RW   2507 arch/powerpc/platforms/cell/spufs/file.c 	u64 mfc_control_RW;
mfc_control_RW   2515 arch/powerpc/platforms/cell/spufs/file.c 		mfc_control_RW = in_be64(&priv2->mfc_control_RW);
mfc_control_RW   2520 arch/powerpc/platforms/cell/spufs/file.c 		mfc_control_RW = csa->priv2.mfc_control_RW;
mfc_control_RW   2535 arch/powerpc/platforms/cell/spufs/file.c 		mfc_control_RW,
mfc_control_RW    305 arch/powerpc/platforms/cell/spufs/hw_ops.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
mfc_control_RW    104 arch/powerpc/platforms/cell/spufs/run.c 	mfc_cntl = &ctx->spu->priv2->mfc_control_RW;
mfc_control_RW    174 arch/powerpc/platforms/cell/spufs/switch.c 	switch (in_be64(&priv2->mfc_control_RW) &
mfc_control_RW    177 arch/powerpc/platforms/cell/spufs/switch.c 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
mfc_control_RW    183 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.mfc_control_RW =
mfc_control_RW    184 arch/powerpc/platforms/cell/spufs/switch.c 				in_be64(&priv2->mfc_control_RW) |
mfc_control_RW    188 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
mfc_control_RW    189 arch/powerpc/platforms/cell/spufs/switch.c 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
mfc_control_RW    193 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.mfc_control_RW =
mfc_control_RW    194 arch/powerpc/platforms/cell/spufs/switch.c 				in_be64(&priv2->mfc_control_RW) &
mfc_control_RW    259 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW &= ~mask;
mfc_control_RW    260 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
mfc_control_RW    271 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW,
mfc_control_RW    342 arch/powerpc/platforms/cell/spufs/switch.c 	if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
mfc_control_RW    464 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW,
mfc_control_RW    478 arch/powerpc/platforms/cell/spufs/switch.c 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
mfc_control_RW    700 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
mfc_control_RW    736 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
mfc_control_RW    970 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
mfc_control_RW    984 arch/powerpc/platforms/cell/spufs/switch.c 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
mfc_control_RW   1263 arch/powerpc/platforms/cell/spufs/switch.c 	if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
mfc_control_RW   1392 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
mfc_control_RW   1425 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
mfc_control_RW   1734 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
mfc_control_RW   2168 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |