meta_req_width    356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int meta_req_width;
meta_req_width    477 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	meta_req_width = 1 << log2_meta_req_width;
meta_req_width    486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
meta_req_width    487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				+ meta_req_width;
meta_req_width    488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
meta_req_width    537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_req_width    356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int meta_req_width;
meta_req_width    477 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	meta_req_width = 1 << log2_meta_req_width;
meta_req_width    486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
meta_req_width    487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				+ meta_req_width;
meta_req_width    488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
meta_req_width    537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_req_width    436 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		unsigned int           meta_req_width[],
meta_req_width   1959 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 				&locals->meta_req_width[k],
meta_req_width   2522 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		locals->meta_req_width,
meta_req_width   4536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 						&locals->meta_req_width[k],
meta_req_width   5824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 		unsigned int meta_req_width[],
meta_req_width   5899 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
meta_req_width    347 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int meta_req_width;
meta_req_width    472 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	meta_req_width = 1 << log2_meta_req_width;
meta_req_width    481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
meta_req_width    482 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				+ meta_req_width;
meta_req_width    483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
meta_req_width    535 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_req_width    583 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 	unsigned int meta_req_width[DC__NUM_DPP__MAX];
meta_req_width    565 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int meta_req_width;
meta_req_width    708 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	meta_req_width = 1 << log2_meta_req_width;
meta_req_width    718 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
meta_req_width    719 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				+ meta_req_width;
meta_req_width    720 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
meta_req_width    764 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;