meta_chunk_threshold  370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int meta_chunk_threshold;
meta_chunk_threshold  512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	meta_chunk_threshold = 0;
meta_chunk_threshold  537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_chunk_threshold  539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
meta_chunk_threshold  541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	if (meta_row_remainder <= meta_chunk_threshold)
meta_chunk_threshold  370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int meta_chunk_threshold;
meta_chunk_threshold  512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	meta_chunk_threshold = 0;
meta_chunk_threshold  537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_chunk_threshold  539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
meta_chunk_threshold  541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	if (meta_row_remainder <= meta_chunk_threshold)
meta_chunk_threshold 5861 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	unsigned int meta_chunk_threshold;
meta_chunk_threshold 5899 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
meta_chunk_threshold 5901 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 				meta_chunk_threshold = 2 * min_meta_chunk_width
meta_chunk_threshold 5904 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 			if (meta_row_remainder <= meta_chunk_threshold) {
meta_chunk_threshold  361 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int meta_chunk_threshold;
meta_chunk_threshold  507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	meta_chunk_threshold = 0;
meta_chunk_threshold  535 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_chunk_threshold  537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
meta_chunk_threshold  539 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	if (meta_row_remainder <= meta_chunk_threshold)
meta_chunk_threshold  577 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int meta_chunk_threshold;
meta_chunk_threshold  742 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	meta_chunk_threshold = 0;
meta_chunk_threshold  764 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
meta_chunk_threshold  766 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
meta_chunk_threshold  768 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (meta_row_remainder <= meta_chunk_threshold)