memory_level 1175 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_MemoryLevel *memory_level memory_level 1187 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); memory_level 1196 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c &memory_level->MinVddci); memory_level 1205 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c &memory_level->MinMvdd); memory_level 1210 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinVddcPhases = 1; memory_level 1214 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_clock, &memory_level->MinVddcPhases); memory_level 1217 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EnabledForThrottle = 1; memory_level 1218 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EnabledForActivity = 1; memory_level 1219 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->UpH = data->current_profile_setting.mclk_up_hyst; memory_level 1220 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->DownH = data->current_profile_setting.mclk_down_hyst; memory_level 1221 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->VoltageDownH = 0; memory_level 1224 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->ActivityLevel = data->current_profile_setting.mclk_activity; memory_level 1225 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StutterEnable = 0; memory_level 1226 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StrobeEnable = 0; memory_level 1227 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EdcReadEnable = 0; memory_level 1228 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EdcWriteEnable = 0; memory_level 1229 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->RttEnable = 0; memory_level 1232 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level 1240 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && memory_level 1245 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock, memory_level 1246 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StrobeEnable); memory_level 1250 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EdcReadEnable = 1; memory_level 1255 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->EdcWriteEnable = 1; memory_level 1258 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (memory_level->StrobeEnable) { memory_level 1267 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->StrobeRatio = memory_level 1273 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); memory_level 1276 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); memory_level 1277 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); memory_level 1278 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); memory_level 1279 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); memory_level 1281 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); memory_level 1283 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); memory_level 1284 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); memory_level 1285 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); memory_level 1286 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); memory_level 1287 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); memory_level 1288 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); memory_level 1289 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); memory_level 1290 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); memory_level 1291 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); memory_level 1292 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); memory_level 1230 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_MemoryLevel *memory_level memory_level 1242 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); memory_level 1248 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddci = memory_level->MinVddc; memory_level 1253 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &memory_level->MinVddci); memory_level 1258 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddcPhases = 1; memory_level 1262 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_clock, &memory_level->MinVddcPhases); memory_level 1265 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EnabledForThrottle = 1; memory_level 1266 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EnabledForActivity = 0; memory_level 1267 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst; memory_level 1268 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst; memory_level 1269 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->VoltageDownHyst = 0; memory_level 1272 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->ActivityLevel = data->current_profile_setting.mclk_activity; memory_level 1273 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StutterEnable = 0; memory_level 1274 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StrobeEnable = 0; memory_level 1275 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EdcReadEnable = 0; memory_level 1276 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EdcWriteEnable = 0; memory_level 1277 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->RttEnable = 0; memory_level 1280 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level 1288 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && memory_level 1293 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock, memory_level 1294 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StrobeEnable); memory_level 1298 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EdcReadEnable = 1; memory_level 1303 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->EdcWriteEnable = 1; memory_level 1306 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (memory_level->StrobeEnable) { memory_level 1315 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->StrobeRatio = memory_level 1321 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); memory_level 1324 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); memory_level 1325 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases); memory_level 1326 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); memory_level 1327 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); memory_level 1329 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); memory_level 1331 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); memory_level 1332 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); memory_level 1333 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); memory_level 1334 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); memory_level 1335 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); memory_level 1336 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); memory_level 1337 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); memory_level 1338 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); memory_level 1339 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); memory_level 1340 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); memory_level 962 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_MemoryLevel *memory_level memory_level 986 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &memory_level->MinVoltage, &mvdd); memory_level 995 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; memory_level 997 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->MinMvdd = mvdd; memory_level 999 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EnabledForThrottle = 1; memory_level 1000 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EnabledForActivity = 0; memory_level 1001 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst; memory_level 1002 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst; memory_level 1003 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->VoltageDownHyst = 0; memory_level 1006 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->ActivityLevel = data->current_profile_setting.mclk_activity; memory_level 1007 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StutterEnable = 0; memory_level 1008 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StrobeEnable = 0; memory_level 1009 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EdcReadEnable = 0; memory_level 1010 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EdcWriteEnable = 0; memory_level 1011 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->RttEnable = 0; memory_level 1014 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level 1025 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StutterEnable = 1; memory_level 1028 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && memory_level 1033 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock, memory_level 1034 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StrobeEnable); memory_level 1038 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EdcReadEnable = 1; memory_level 1043 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->EdcWriteEnable = 1; memory_level 1046 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if (memory_level->StrobeEnable) { memory_level 1058 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_level->StrobeRatio = memory_level 1064 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); memory_level 1067 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd); memory_level 1069 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); memory_level 1071 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); memory_level 1072 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); memory_level 1073 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); memory_level 1074 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); memory_level 1075 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); memory_level 1076 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); memory_level 1077 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); memory_level 1078 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); memory_level 1079 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); memory_level 1080 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); memory_level 2877 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MemoryLevel *memory_level) memory_level 2886 drivers/gpu/drm/radeon/ci_dpm.c memory_clock, &memory_level->MinVddc); memory_level 2894 drivers/gpu/drm/radeon/ci_dpm.c memory_clock, &memory_level->MinVddci); memory_level 2902 drivers/gpu/drm/radeon/ci_dpm.c memory_clock, &memory_level->MinMvdd); memory_level 2907 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MinVddcPhases = 1; memory_level 2913 drivers/gpu/drm/radeon/ci_dpm.c &memory_level->MinVddcPhases); memory_level 2915 drivers/gpu/drm/radeon/ci_dpm.c memory_level->EnabledForThrottle = 1; memory_level 2916 drivers/gpu/drm/radeon/ci_dpm.c memory_level->UpH = 0; memory_level 2917 drivers/gpu/drm/radeon/ci_dpm.c memory_level->DownH = 100; memory_level 2918 drivers/gpu/drm/radeon/ci_dpm.c memory_level->VoltageDownH = 0; memory_level 2919 drivers/gpu/drm/radeon/ci_dpm.c memory_level->ActivityLevel = (u16)pi->mclk_activity_target; memory_level 2921 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StutterEnable = false; memory_level 2922 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StrobeEnable = false; memory_level 2923 drivers/gpu/drm/radeon/ci_dpm.c memory_level->EdcReadEnable = false; memory_level 2924 drivers/gpu/drm/radeon/ci_dpm.c memory_level->EdcWriteEnable = false; memory_level 2925 drivers/gpu/drm/radeon/ci_dpm.c memory_level->RttEnable = false; memory_level 2927 drivers/gpu/drm/radeon/ci_dpm.c memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; memory_level 2934 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StutterEnable = true; memory_level 2938 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StrobeEnable = 1; memory_level 2941 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StrobeRatio = memory_level 2942 drivers/gpu/drm/radeon/ci_dpm.c si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); memory_level 2945 drivers/gpu/drm/radeon/ci_dpm.c memory_level->EdcReadEnable = true; memory_level 2949 drivers/gpu/drm/radeon/ci_dpm.c memory_level->EdcWriteEnable = true; memory_level 2951 drivers/gpu/drm/radeon/ci_dpm.c if (memory_level->StrobeEnable) { memory_level 2961 drivers/gpu/drm/radeon/ci_dpm.c memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock); memory_level 2965 drivers/gpu/drm/radeon/ci_dpm.c ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); memory_level 2969 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); memory_level 2970 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); memory_level 2971 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); memory_level 2972 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); memory_level 2974 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); memory_level 2975 drivers/gpu/drm/radeon/ci_dpm.c memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); memory_level 2976 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); memory_level 2977 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); memory_level 2978 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); memory_level 2979 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); memory_level 2980 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); memory_level 2981 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); memory_level 2982 drivers/gpu/drm/radeon/ci_dpm.c memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); memory_level 2983 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); memory_level 2984 drivers/gpu/drm/radeon/ci_dpm.c memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);