mem_timings        39 arch/arm/mach-omap2/sdrc2xxx.c static struct memory_timings mem_timings;
mem_timings        44 arch/arm/mach-omap2/sdrc2xxx.c 	return mem_timings.slow_dll_ctrl;
mem_timings        49 arch/arm/mach-omap2/sdrc2xxx.c 	return mem_timings.fast_dll_ctrl;
mem_timings        54 arch/arm/mach-omap2/sdrc2xxx.c 	return mem_timings.m_type;
mem_timings       120 arch/arm/mach-omap2/sdrc2xxx.c 	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
mem_timings       126 arch/arm/mach-omap2/sdrc2xxx.c 		mem_timings.base_cs = 1;
mem_timings       128 arch/arm/mach-omap2/sdrc2xxx.c 		mem_timings.base_cs = 0;
mem_timings       130 arch/arm/mach-omap2/sdrc2xxx.c 	if (mem_timings.m_type != M_DDR)
mem_timings       134 arch/arm/mach-omap2/sdrc2xxx.c 	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
mem_timings       135 arch/arm/mach-omap2/sdrc2xxx.c 		mem_timings.dll_mode = M_UNLOCK;
mem_timings       137 arch/arm/mach-omap2/sdrc2xxx.c 		mem_timings.dll_mode = M_LOCK;
mem_timings       139 arch/arm/mach-omap2/sdrc2xxx.c 	if (mem_timings.base_cs == 0) {
mem_timings       151 arch/arm/mach-omap2/sdrc2xxx.c 	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
mem_timings       154 arch/arm/mach-omap2/sdrc2xxx.c 	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
mem_timings       155 arch/arm/mach-omap2/sdrc2xxx.c 			    mem_timings.fast_dll_ctrl,
mem_timings       156 arch/arm/mach-omap2/sdrc2xxx.c 			    mem_timings.base_cs,
mem_timings       158 arch/arm/mach-omap2/sdrc2xxx.c 	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */
mem_timings       161 arch/arm/mach-omap2/sdrc2xxx.c 	mem_timings.slow_dll_ctrl |=
mem_timings       162 arch/arm/mach-omap2/sdrc2xxx.c 		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
mem_timings       165 arch/arm/mach-omap2/sdrc2xxx.c 	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));