mem_level        1166 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
mem_level        1183 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
mem_level        1189 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->EnabledForThrottle = 1;
mem_level        1190 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->EnabledForActivity = 0;
mem_level        1191 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
mem_level        1192 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
mem_level        1193 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->VoltageDownHyst = 0;
mem_level        1194 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
mem_level        1195 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->StutterEnable = false;
mem_level        1197 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
mem_level        1211 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		mem_level->StutterEnable = true;
mem_level        1213 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
mem_level        1215 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
mem_level        1216 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
mem_level        1217 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
mem_level        1218 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
mem_level        1072 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
mem_level        1090 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				&mem_level->MinVoltage, &mem_level->MinMvdd);
mem_level        1096 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->MclkFrequency = clock;
mem_level        1097 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->EnabledForThrottle = 1;
mem_level        1098 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->EnabledForActivity = 0;
mem_level        1099 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
mem_level        1100 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
mem_level        1101 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->VoltageDownHyst = 0;
mem_level        1102 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
mem_level        1103 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->StutterEnable = false;
mem_level        1104 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
mem_level        1113 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		mem_level->StutterEnable = true;
mem_level        1116 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
mem_level        1117 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
mem_level        1118 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
mem_level        1119 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
mem_level         961 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
mem_level         970 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
mem_level         971 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
mem_level         972 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
mem_level         973 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
mem_level         979 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
mem_level         991 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				&mem_level->MinVoltage, &mem_level->MinMvdd);
mem_level         997 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
mem_level        1002 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->EnabledForThrottle = 1;
mem_level        1003 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->EnabledForActivity = 0;
mem_level        1004 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->VoltageDownHyst = 0;
mem_level        1005 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->ActivityLevel = (uint16_t)
mem_level        1007 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->StutterEnable = false;
mem_level        1008 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
mem_level        1017 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		mem_level->StutterEnable = true;
mem_level        1020 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
mem_level        1021 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
mem_level        1022 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
mem_level        1023 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
mem_level        1024 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
mem_level        1025 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);