mem_fclk_21285     24 arch/arm/include/asm/system_info.h extern unsigned int mem_fclk_21285;
mem_fclk_21285     67 arch/arm/kernel/atags_compat.c 	    unsigned long mem_fclk_21285;       /* 88 */
mem_fclk_21285    161 arch/arm/kernel/atags_compat.c 	if (params->u1.s.mem_fclk_21285) {
mem_fclk_21285    165 arch/arm/kernel/atags_compat.c 		tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285;
mem_fclk_21285     31 arch/arm/mach-footbridge/common.c unsigned int mem_fclk_21285 = 50000000;
mem_fclk_21285     33 arch/arm/mach-footbridge/common.c EXPORT_SYMBOL(mem_fclk_21285);
mem_fclk_21285     37 arch/arm/mach-footbridge/common.c 	mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
mem_fclk_21285     45 arch/arm/mach-footbridge/common.c 	mem_fclk_21285 = tag->u.memclk.fmemclk;
mem_fclk_21285     70 arch/arm/mach-footbridge/dc21285-timer.c 	*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
mem_fclk_21285    117 arch/arm/mach-footbridge/dc21285-timer.c 	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
mem_fclk_21285    134 arch/arm/mach-footbridge/dc21285-timer.c 	unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
mem_fclk_21285     24 drivers/tty/serial/21285.c #define BAUD_BASE		(mem_fclk_21285/64)
mem_fclk_21285    367 drivers/tty/serial/21285.c 	serial21285_port.uartclk = mem_fclk_21285 / 4;
mem_fclk_21285     77 drivers/watchdog/wdt285.c 	reload = soft_margin * (mem_fclk_21285 / 256);
mem_fclk_21285    169 drivers/watchdog/wdt285.c 		reload = soft_margin * (mem_fclk_21285 / 256);