mem_access_subid  701 arch/mips/pci/pcie-octeon.c 	union cvmx_npei_mem_access_subidx mem_access_subid;
mem_access_subid  889 arch/mips/pci/pcie-octeon.c 	mem_access_subid.u64 = 0;
mem_access_subid  890 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
mem_access_subid  891 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.nmerge = 1;	/* Due to an errata on pass 1 chips, no merging is allowed. */
mem_access_subid  892 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */
mem_access_subid  893 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */
mem_access_subid  894 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.nsr = 0;	/* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
mem_access_subid  895 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.nsw = 0;	/* Enable Snoop for Writes. */
mem_access_subid  896 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.ror = 0;	/* Disable Relaxed Ordering for Reads. */
mem_access_subid  897 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.row = 0;	/* Disable Relaxed Ordering for Writes. */
mem_access_subid  898 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.ba = 0;	/* PCIe Adddress Bits <63:34>. */
mem_access_subid  905 arch/mips/pci/pcie-octeon.c 		cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
mem_access_subid  906 arch/mips/pci/pcie-octeon.c 		mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
mem_access_subid 1160 arch/mips/pci/pcie-octeon.c 	union cvmx_sli_mem_access_subidx mem_access_subid;
mem_access_subid 1341 arch/mips/pci/pcie-octeon.c 	mem_access_subid.u64 = 0;
mem_access_subid 1342 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
mem_access_subid 1343 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.nmerge = 0;	/* Allow merging as it works on CN6XXX. */
mem_access_subid 1344 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */
mem_access_subid 1345 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */
mem_access_subid 1346 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.wtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid 1347 arch/mips/pci/pcie-octeon.c 	mem_access_subid.s.rtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid 1350 arch/mips/pci/pcie-octeon.c 		mem_access_subid.cn68xx.ba = 0;
mem_access_subid 1352 arch/mips/pci/pcie-octeon.c 		mem_access_subid.s.ba = 0;
mem_access_subid 1359 arch/mips/pci/pcie-octeon.c 		cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
mem_access_subid 1361 arch/mips/pci/pcie-octeon.c 		__cvmx_increment_ba(&mem_access_subid);