mec_int_cntl_reg 4899 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl_reg 4910 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
mec_int_cntl_reg 4913 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
mec_int_cntl_reg 4916 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
mec_int_cntl_reg 4919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
mec_int_cntl_reg 4932 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 4935 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 4938 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 4941 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 4727 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl_reg 4738 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
mec_int_cntl_reg 4741 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
mec_int_cntl_reg 4744 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
mec_int_cntl_reg 4747 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
mec_int_cntl_reg 4760 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 4762 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 4765 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 4767 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 6548 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl_reg 6559 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
mec_int_cntl_reg 6562 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
mec_int_cntl_reg 6565 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
mec_int_cntl_reg 6568 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
mec_int_cntl_reg 6581 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 6583 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 6586 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 6588 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 5498 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl_reg 5509 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
mec_int_cntl_reg 5512 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
mec_int_cntl_reg 5515 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
mec_int_cntl_reg 5518 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
mec_int_cntl_reg 5531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 5534 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl_reg 5537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl_reg 5540 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);