mec_int_cntl     4899 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl     4932 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     4933 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
mec_int_cntl     4935 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     4938 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     4939 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
mec_int_cntl     4941 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     4727 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl     4760 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     4761 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
mec_int_cntl     4762 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     4765 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     4766 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
mec_int_cntl     4767 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     6548 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl     6581 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     6582 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
mec_int_cntl     6583 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     6586 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     6587 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
mec_int_cntl     6588 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     5498 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	u32 mec_int_cntl, mec_int_cntl_reg;
mec_int_cntl     5531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     5532 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
mec_int_cntl     5534 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);
mec_int_cntl     5537 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = RREG32(mec_int_cntl_reg);
mec_int_cntl     5538 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
mec_int_cntl     5540 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(mec_int_cntl_reg, mec_int_cntl);