me_cntl           406 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	u32 me_cntl;
me_cntl           415 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
me_cntl           417 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
me_cntl           419 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
me_cntl           420 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
me_cntl           333 drivers/gpu/drm/radeon/cik_sdma.c 	u32 me_cntl, reg_offset;
me_cntl           346 drivers/gpu/drm/radeon/cik_sdma.c 		me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
me_cntl           348 drivers/gpu/drm/radeon/cik_sdma.c 			me_cntl &= ~SDMA_HALT;
me_cntl           350 drivers/gpu/drm/radeon/cik_sdma.c 			me_cntl |= SDMA_HALT;
me_cntl           351 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);