mdr               411 arch/arm/mach-at91/pm.c 	u32 mdr, saved_mdr0, saved_mdr1 = 0;
mdr               417 arch/arm/mach-at91/pm.c 		mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
mdr               418 arch/arm/mach-at91/pm.c 		mdr |= AT91_DDRSDRC_MD_DDR2;
mdr               419 arch/arm/mach-at91/pm.c 		at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
mdr               428 arch/arm/mach-at91/pm.c 			mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
mdr               429 arch/arm/mach-at91/pm.c 			mdr |= AT91_DDRSDRC_MD_DDR2;
mdr               430 arch/arm/mach-at91/pm.c 			at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
mdr               105 arch/powerpc/include/asm/fsl_lbc.h 	__be32 mdr;             /**< UPM Data Register */
mdr                71 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
mdr                83 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
mdr                96 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
mdr               201 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
mdr               208 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
mdr               215 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
mdr                39 arch/x86/platform/intel/iosf_mbi.c static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
mdr                57 arch/x86/platform/intel/iosf_mbi.c 	result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
mdr                68 arch/x86/platform/intel/iosf_mbi.c static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
mdr                75 arch/x86/platform/intel/iosf_mbi.c 	result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
mdr                97 arch/x86/platform/intel/iosf_mbi.c int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
mdr               113 arch/x86/platform/intel/iosf_mbi.c 	ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
mdr               120 arch/x86/platform/intel/iosf_mbi.c int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
mdr               136 arch/x86/platform/intel/iosf_mbi.c 	ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
mdr               143 arch/x86/platform/intel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
mdr               170 arch/x86/platform/intel/iosf_mbi.c 	mdr &= mask;
mdr               171 arch/x86/platform/intel/iosf_mbi.c 	value |= mdr;
mdr               353 drivers/media/platform/rcar_drif.c 		u32 mdr;
mdr               356 drivers/media/platform/rcar_drif.c 		mdr = RCAR_DRIF_MDR_GRPCNT(2) |
mdr               359 drivers/media/platform/rcar_drif.c 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
mdr               361 drivers/media/platform/rcar_drif.c 		mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
mdr               363 drivers/media/platform/rcar_drif.c 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
mdr                60 drivers/mtd/nand/raw/fsl_elbc_nand.c 	unsigned int mdr;        /* UPM/FCM Data Register value           */
mdr               214 drivers/mtd/nand/raw/fsl_elbc_nand.c 		out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
mdr               235 drivers/mtd/nand/raw/fsl_elbc_nand.c 		elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
mdr               243 drivers/mtd/nand/raw/fsl_elbc_nand.c 			 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
mdr               384 drivers/mtd/nand/raw/fsl_elbc_nand.c 		elbc_fcm_ctrl->mdr = column;
mdr               631 drivers/mtd/nand/raw/fsl_elbc_nand.c 	return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
mdr               187 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c 	int mdr;
mdr               199 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c 	mdr = (GDC_ROP_COPY << 9);