mdp5_cstate        89 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate        90 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_cstate        91 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate        92 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	bool start = !mdp5_cstate->defer_start;
mdp5_cstate        94 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate->defer_start = false;
mdp5_cstate       108 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       114 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (WARN_ON(!mdp5_cstate->ctl))
mdp5_cstate       123 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mixer = mdp5_cstate->pipeline.mixer;
mdp5_cstate       126 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	r_mixer = mdp5_cstate->pipeline.r_mixer;
mdp5_cstate       136 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       137 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate       139 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_cstate       213 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       214 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate       224 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_cstate       365 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       367 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
mdp5_cstate       368 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
mdp5_cstate       415 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       428 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->cmd_mode)
mdp5_cstate       447 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       448 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
mdp5_cstate       461 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       484 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
mdp5_cstate       485 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 					    &mdp5_cstate->pipeline, 0, true);
mdp5_cstate       487 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
mdp5_cstate       488 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 					    &mdp5_cstate->pipeline, 0, false);
mdp5_cstate       499 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->cmd_mode)
mdp5_cstate       509 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate =
mdp5_cstate       511 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate       551 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate->err_irqmask = intf2err(intf->num);
mdp5_cstate       552 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
mdp5_cstate       556 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
mdp5_cstate       557 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		mdp5_cstate->cmd_mode = true;
mdp5_cstate       559 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		mdp5_cstate->pp_done_irqmask = 0;
mdp5_cstate       560 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		mdp5_cstate->cmd_mode = false;
mdp5_cstate       591 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate =
mdp5_cstate       598 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->pipeline.r_mixer)
mdp5_cstate       707 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       726 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (unlikely(!mdp5_cstate->ctl))
mdp5_cstate       737 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->cmd_mode)
mdp5_cstate       743 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
mdp5_cstate       744 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
mdp5_cstate       745 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
mdp5_cstate       790 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       801 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	lm = mdp5_cstate->pipeline.mixer->lm;
mdp5_cstate       860 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       861 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate       884 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	ctl = mdp5_cstate->ctl;
mdp5_cstate       889 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->pipeline.r_mixer)
mdp5_cstate       946 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate       960 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->pipeline.r_mixer)
mdp5_cstate       990 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
mdp5_cstate       991 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
mdp5_cstate       997 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->ctl)
mdp5_cstate       998 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
mdp5_cstate      1007 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
mdp5_cstate      1013 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate;
mdp5_cstate      1018 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
mdp5_cstate      1019 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			      sizeof(*mdp5_cstate), GFP_KERNEL);
mdp5_cstate      1020 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (!mdp5_cstate)
mdp5_cstate      1023 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	__drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
mdp5_cstate      1025 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return &mdp5_cstate->base;
mdp5_cstate      1030 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
mdp5_cstate      1034 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	kfree(mdp5_cstate);
mdp5_cstate      1039 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate =
mdp5_cstate      1040 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
mdp5_cstate      1045 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	__drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
mdp5_cstate      1109 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1116 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 				     mdp5_cstate->pipeline.mixer->lm);
mdp5_cstate      1123 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1124 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
mdp5_cstate      1155 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1161 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
mdp5_cstate      1166 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1168 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return mdp5_cstate->ctl;
mdp5_cstate      1173 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate;
mdp5_cstate      1178 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1180 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
mdp5_cstate      1181 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
mdp5_cstate      1186 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate;
mdp5_cstate      1191 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1193 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return &mdp5_cstate->pipeline;
mdp5_cstate      1198 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
mdp5_cstate      1200 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mdp5_cstate->cmd_mode)
mdp5_cstate       298 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
mdp5_cstate       302 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_cstate->ctl = ctl;
mdp5_cstate       303 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_cstate->pipeline.intf = intf;
mdp5_cstate       314 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 		mdp5_cstate->defer_start = true;