mdp5_cmd_enc 22 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c static void bs_set(struct mdp5_encoder *mdp5_cmd_enc, int idx) mdp5_cmd_enc 24 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c if (mdp5_cmd_enc->bsc) { mdp5_cmd_enc 31 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c msm_bus_scale_client_update_request(mdp5_cmd_enc->bsc, idx); mdp5_cmd_enc 35 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c static void bs_set(struct mdp5_encoder *mdp5_cmd_enc, int idx) {} mdp5_cmd_enc 136 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); mdp5_cmd_enc 137 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl; mdp5_cmd_enc 138 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_interface *intf = mdp5_cmd_enc->intf; mdp5_cmd_enc 141 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c if (WARN_ON(!mdp5_cmd_enc->enabled)) mdp5_cmd_enc 149 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c bs_set(mdp5_cmd_enc, 0); mdp5_cmd_enc 151 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_cmd_enc->enabled = false; mdp5_cmd_enc 156 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); mdp5_cmd_enc 157 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl; mdp5_cmd_enc 158 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_interface *intf = mdp5_cmd_enc->intf; mdp5_cmd_enc 161 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c if (WARN_ON(mdp5_cmd_enc->enabled)) mdp5_cmd_enc 164 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c bs_set(mdp5_cmd_enc, 1); mdp5_cmd_enc 172 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_cmd_enc->enabled = true; mdp5_cmd_enc 178 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); mdp5_cmd_enc 188 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c intf_num = mdp5_cmd_enc->intf->num;