mcuclk            296 drivers/soc/xilinx/xlnx_vcu.c 	u32 refclk, coreclk, mcuclk, inte, deci;
mcuclk            306 drivers/soc/xilinx/xlnx_vcu.c 	mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ;
mcuclk            307 drivers/soc/xilinx/xlnx_vcu.c 	if (!mcuclk || !coreclk) {
mcuclk            315 drivers/soc/xilinx/xlnx_vcu.c 	dev_dbg(xvcu->dev, "Mcu clock from logicoreIP is %uHz\n", mcuclk);
mcuclk            363 drivers/soc/xilinx/xlnx_vcu.c 				divisor_mcu = pll_clk / mcuclk;
mcuclk            364 drivers/soc/xilinx/xlnx_vcu.c 				mod = pll_clk % mcuclk;
mcuclk            365 drivers/soc/xilinx/xlnx_vcu.c 				if (mcuclk - mod < LIMIT)
mcuclk            378 drivers/soc/xilinx/xlnx_vcu.c 	mcuclk = pll_clk / divisor_mcu;
mcuclk            381 drivers/soc/xilinx/xlnx_vcu.c 	dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk);