mcode             695 arch/arm/mach-omap2/vc.c 	u8 mcode;
mcode             717 arch/arm/mach-omap2/vc.c 	mcode = voltdm->pmic->i2c_mcode;
mcode             718 arch/arm/mach-omap2/vc.c 	if (mcode)
mcode             720 arch/arm/mach-omap2/vc.c 			    mcode << __ffs(vc->common->i2c_mcode_mask),
mcode              53 drivers/crypto/cavium/cpt/cptpf.h 	struct microcode mcode[CPT_MAX_CORE_GROUPS];
mcode             123 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
mcode             129 drivers/crypto/cavium/cpt/cptpf_main.c 	if (!mcode || !mcode->code) {
mcode             134 drivers/crypto/cavium/cpt/cptpf_main.c 	if (mcode->code_size == 0) {
mcode             142 drivers/crypto/cavium/cpt/cptpf_main.c 	if (mcode->is_ae) {
mcode             152 drivers/crypto/cavium/cpt/cptpf_main.c 		if (mcode->core_mask & (1 << shift)) {
mcode             155 drivers/crypto/cavium/cpt/cptpf_main.c 					(u64)mcode->phys_base);
mcode             161 drivers/crypto/cavium/cpt/cptpf_main.c static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
mcode             171 drivers/crypto/cavium/cpt/cptpf_main.c 	if (mcode->is_ae) {
mcode             172 drivers/crypto/cavium/cpt/cptpf_main.c 		if (mcode->num_cores > cpt->max_ae_cores) {
mcode             183 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->group = cpt->next_group;
mcode             185 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
mcode             186 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES,
mcode             187 drivers/crypto/cavium/cpt/cptpf_main.c 				  mcode->group);
mcode             189 drivers/crypto/cavium/cpt/cptpf_main.c 		ret = cpt_load_microcode(cpt, mcode);
mcode             192 drivers/crypto/cavium/cpt/cptpf_main.c 				mcode->version);
mcode             197 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
mcode             200 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES);
mcode             202 drivers/crypto/cavium/cpt/cptpf_main.c 		if (mcode->num_cores > cpt->max_se_cores) {
mcode             212 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->group = cpt->next_group;
mcode             214 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
mcode             215 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES,
mcode             216 drivers/crypto/cavium/cpt/cptpf_main.c 				  mcode->group);
mcode             218 drivers/crypto/cavium/cpt/cptpf_main.c 		ret = cpt_load_microcode(cpt, mcode);
mcode             221 drivers/crypto/cavium/cpt/cptpf_main.c 				mcode->version);
mcode             226 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
mcode             229 drivers/crypto/cavium/cpt/cptpf_main.c 		cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES);
mcode             257 drivers/crypto/cavium/cpt/cptpf_main.c 	struct microcode *mcode;
mcode             265 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode = &cpt->mcode[cpt->next_mc_idx];
mcode             266 drivers/crypto/cavium/cpt/cptpf_main.c 	memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ);
mcode             267 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->code_size = ntohl(ucode->code_length) * 2;
mcode             268 drivers/crypto/cavium/cpt/cptpf_main.c 	if (!mcode->code_size) {
mcode             273 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->is_ae = is_ae;
mcode             274 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->core_mask = 0ULL;
mcode             275 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->num_cores = is_ae ? 6 : 10;
mcode             278 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->code = dma_alloc_coherent(&cpt->pdev->dev, mcode->code_size,
mcode             279 drivers/crypto/cavium/cpt/cptpf_main.c 					 &mcode->phys_base, GFP_KERNEL);
mcode             280 drivers/crypto/cavium/cpt/cptpf_main.c 	if (!mcode->code) {
mcode             286 drivers/crypto/cavium/cpt/cptpf_main.c 	memcpy((void *)mcode->code, (void *)(fw_entry->data + sizeof(*ucode)),
mcode             287 drivers/crypto/cavium/cpt/cptpf_main.c 	       mcode->code_size);
mcode             290 drivers/crypto/cavium/cpt/cptpf_main.c 	for (j = 0; j < (mcode->code_size / 8); j++)
mcode             291 drivers/crypto/cavium/cpt/cptpf_main.c 		((u64 *)mcode->code)[j] = cpu_to_be64(((u64 *)mcode->code)[j]);
mcode             293 drivers/crypto/cavium/cpt/cptpf_main.c 	for (j = 0; j < (mcode->code_size / 2); j++)
mcode             294 drivers/crypto/cavium/cpt/cptpf_main.c 		((u16 *)mcode->code)[j] = cpu_to_be16(((u16 *)mcode->code)[j]);
mcode             296 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_dbg(dev, "mcode->code_size = %u\n", mcode->code_size);
mcode             297 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_dbg(dev, "mcode->is_ae = %u\n", mcode->is_ae);
mcode             298 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_dbg(dev, "mcode->num_cores = %u\n", mcode->num_cores);
mcode             299 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_dbg(dev, "mcode->code = %llx\n", (u64)mcode->code);
mcode             300 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_dbg(dev, "mcode->phys_base = %llx\n", mcode->phys_base);
mcode             302 drivers/crypto/cavium/cpt/cptpf_main.c 	ret = do_cpt_init(cpt, mcode);
mcode             308 drivers/crypto/cavium/cpt/cptpf_main.c 	dev_info(dev, "Microcode Loaded %s\n", mcode->version);
mcode             309 drivers/crypto/cavium/cpt/cptpf_main.c 	mcode->is_mc_valid = 1;
mcode             416 drivers/crypto/cavium/cpt/cptpf_main.c 		struct microcode *mcode = &cpt->mcode[grp];
mcode             418 drivers/crypto/cavium/cpt/cptpf_main.c 		if (cpt->mcode[grp].code)
mcode             419 drivers/crypto/cavium/cpt/cptpf_main.c 			dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
mcode             420 drivers/crypto/cavium/cpt/cptpf_main.c 					  mcode->code, mcode->phys_base);
mcode             421 drivers/crypto/cavium/cpt/cptpf_main.c 		mcode->code = NULL;
mcode              61 drivers/crypto/cavium/cpt/cptpf_mbox.c 	struct microcode *mcode = cpt->mcode;
mcode              78 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.s.grp = mcode[grp].group;
mcode              80 drivers/crypto/cavium/cpt/cptpf_mbox.c 	dev_dbg(dev, "VF %d TYPE %s", q, (mcode[grp].is_ae ? "AE" : "SE"));
mcode              82 drivers/crypto/cavium/cpt/cptpf_mbox.c 	return mcode[grp].is_ae ? AE_TYPES : SE_TYPES;
mcode            1001 drivers/infiniband/hw/ocrdma/ocrdma_hw.c 	u8 mcode;
mcode            1008 drivers/infiniband/hw/ocrdma/ocrdma_hw.c 		mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
mcode            1010 drivers/infiniband/hw/ocrdma/ocrdma_hw.c 		if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
mcode             294 sound/isa/sb/sb16_csp.c 				struct snd_sb_csp_microcode __user * mcode)
mcode             309 sound/isa/sb/sb16_csp.c 	if (copy_from_user(&info, mcode, sizeof(info)))
mcode             311 sound/isa/sb/sb16_csp.c 	data_ptr = mcode->data;