mcmtr 135 drivers/edac/i10nm_base.c u32 mcmtr; mcmtr 137 drivers/edac/i10nm_base.c mcmtr = *(u32 *)(imc->mbase + 0x20ef8 + chan * 0x4000); mcmtr 138 drivers/edac/i10nm_base.c edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr); mcmtr 140 drivers/edac/i10nm_base.c return !!GET_BITFIELD(mcmtr, 2, 2); mcmtr 196 drivers/edac/sb_edac.c #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) mcmtr 197 drivers/edac/sb_edac.c #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) mcmtr 198 drivers/edac/sb_edac.c #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) mcmtr 314 drivers/edac/sb_edac.c u32 mcmtr; mcmtr 1633 drivers/edac/sb_edac.c if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { mcmtr 1699 drivers/edac/sb_edac.c if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { mcmtr 1729 drivers/edac/sb_edac.c if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { mcmtr 1733 drivers/edac/sb_edac.c if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { mcmtr 1742 drivers/edac/sb_edac.c if (IS_CLOSE_PG(pvt->info.mcmtr)) { mcmtr 154 drivers/edac/skx_base.c static bool skx_check_ecc(u32 mcmtr) mcmtr 156 drivers/edac/skx_base.c return !!GET_BITFIELD(mcmtr, 2, 2); mcmtr 162 drivers/edac/skx_base.c u32 mtr, mcmtr, amap, mcddrtcfg; mcmtr 169 drivers/edac/skx_base.c pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr); mcmtr 181 drivers/edac/skx_base.c ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j); mcmtr 188 drivers/edac/skx_base.c if (ndimms && !skx_check_ecc(mcmtr)) { mcmtr 286 drivers/edac/skx_common.c int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, mcmtr 306 drivers/edac/skx_common.c imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0); mcmtr 307 drivers/edac/skx_common.c imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9); mcmtr 129 drivers/edac/skx_common.h int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,