mclk_table 374 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c phm_ppt_v1_clock_voltage_dependency_table *mclk_table; mclk_table 384 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c mclk_table = kzalloc(table_size, GFP_KERNEL); mclk_table 386 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if (NULL == mclk_table) mclk_table 389 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; mclk_table 394 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c entries, mclk_table, i); mclk_table 405 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c *pp_tonga_mclk_dep_table = mclk_table; mclk_table 834 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c struct smu10_voltage_dependency_table *mclk_table = mclk_table 862 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c if (low > mclk_table->count - 1 || high > mclk_table->count - 1) mclk_table 867 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c mclk_table->entries[low].clk/100); mclk_table 871 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c mclk_table->entries[high].clk/100); mclk_table 885 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c struct smu10_voltage_dependency_table *mclk_table = mclk_table 916 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c for (i = 0; i < mclk_table->count; i++) mclk_table 919 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c mclk_table->entries[i].clk / 100, mclk_table 920 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ((mclk_table->entries[i].clk / 100) mclk_table 638 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &data->dpm_table.mclk_table, mclk_table 706 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.count = 0; mclk_table 708 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != mclk_table 710 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = mclk_table 712 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; mclk_table 713 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.count++; mclk_table 801 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.count = 0; mclk_table 803 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i == 0 || data->dpm_table.mclk_table.dpm_levels mclk_table 804 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c [data->dpm_table.mclk_table.count - 1].value != mclk_table 806 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = mclk_table 808 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = mclk_table 810 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.count++; mclk_table 850 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.mclk_table.count; mclk_table 852 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) { mclk_table 853 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; mclk_table 914 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < data->dpm_table.mclk_table.count; i++) { mclk_table 916 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.mclk_table.dpm_levels[i].value) { mclk_table 1853 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = mclk_table 1872 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { mclk_table 1873 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c voltage_id = mclk_table->entries[entry_id].vddInd; mclk_table 1874 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->entries[entry_id].vddc = mclk_table 1933 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; mclk_table 1951 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { mclk_table 1952 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) mclk_table 1953 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c v_record.us_vdd = mclk_table->entries[entry_id].vddc + mclk_table 1954 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->entries[entry_id].vdd_offset - 0xFFFF; mclk_table 1956 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c v_record.us_vdd = mclk_table->entries[entry_id].vddc + mclk_table 1957 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->entries[entry_id].vdd_offset; mclk_table 1959 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = mclk_table 2737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (golden_dpm_table->mclk_table.count < 1) mclk_table 2741 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; mclk_table 2743 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (golden_dpm_table->mclk_table.count == 1) { mclk_table 2745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; mclk_table 2746 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *mclk_mask = golden_dpm_table->mclk_table.count - 1; mclk_table 2748 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; mclk_table 2749 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *mclk_mask = golden_dpm_table->mclk_table.count - 2; mclk_table 2793 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *mclk_mask = golden_dpm_table->mclk_table.count - 1; mclk_table 3602 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); mclk_table 3628 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < mclk_table->count; i++) { mclk_table 3629 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (mclk == mclk_table->dpm_levels[i].value) mclk_table 3633 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i >= mclk_table->count) { mclk_table 3634 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (mclk > mclk_table->dpm_levels[i-1].value) { mclk_table 3636 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->dpm_levels[i-1].value = mclk; mclk_table 3776 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (count = 0; count < dpm_table->mclk_table.count; count++) { mclk_table 3777 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; mclk_table 3778 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; mclk_table 3841 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->dpm_table.mclk_table), mclk_table 3866 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); mclk_table 4446 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); mclk_table 4475 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < mclk_table->count; i++) { mclk_table 4476 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (clock > mclk_table->dpm_levels[i].value) mclk_table 4482 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < mclk_table->count; i++) mclk_table 4484 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c i, mclk_table->dpm_levels[i].value / 100, mclk_table 4528 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, mclk_table 4611 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); mclk_table 4613 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->golden_dpm_table.mclk_table); mclk_table 4614 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c int value = mclk_table->dpm_levels[mclk_table->count - 1].value; mclk_table 4628 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->golden_dpm_table.mclk_table); mclk_table 4694 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_clock_voltage_dependency_table *mclk_table; mclk_table 4707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; mclk_table 4708 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < mclk_table->count; i++) mclk_table 4709 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = mclk_table->entries[i].clk * 10; mclk_table 4710 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = mclk_table->count; mclk_table 4778 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); mclk_table 4783 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->memory_max_clock = mclk_table->count > 1 ? mclk_table 4784 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->dpm_levels[mclk_table->count-1].value : mclk_table 4785 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c mclk_table->dpm_levels[0].value; mclk_table 4834 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || mclk_table 4837 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, mclk_table 105 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h struct smu7_single_dpm_table mclk_table; mclk_table 667 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = mclk_table 694 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { mclk_table 695 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c voltage_id = mclk_table->entries[entry_id].vddInd; mclk_table 696 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mclk_table->entries[entry_id].vddc = mclk_table 698 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c voltage_id = mclk_table->entries[entry_id].vddciInd; mclk_table 699 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mclk_table->entries[entry_id].vddci = mclk_table 701 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c voltage_id = mclk_table->entries[entry_id].mvddInd; mclk_table 702 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mclk_table->entries[entry_id].mvdd = mclk_table 3293 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); mclk_table 3310 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (i = 0; i < mclk_table->count; i++) { mclk_table 3311 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (mclk == mclk_table->dpm_levels[i].value) mclk_table 3315 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (i >= mclk_table->count) { mclk_table 3316 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (mclk > mclk_table->dpm_levels[i-1].value) { mclk_table 3318 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mclk_table->dpm_levels[i-1].value = mclk; mclk_table 3891 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, mclk_table 3897 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (mclk_table == NULL || mclk_table->count == 0) mclk_table 3900 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c count = (uint8_t)(mclk_table->count); mclk_table 3903 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if(mclk_table->entries[i].clk >= frequency) mclk_table 3918 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; mclk_table 3955 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); mclk_table 4472 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); mclk_table 4500 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (i = 0; i < mclk_table->count; i++) mclk_table 4502 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c i, mclk_table->dpm_levels[i].value / 100, mclk_table 4802 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); mclk_table 4805 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int value = mclk_table->dpm_levels[mclk_table->count - 1].value; mclk_table 609 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c phm_ppt_v1_clock_voltage_dependency_table *mclk_table; mclk_table 618 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table = kzalloc(table_size, GFP_KERNEL); mclk_table 620 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c if (!mclk_table) mclk_table 623 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; mclk_table 626 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->entries[i].vddInd = mclk_table 628 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->entries[i].vddciInd = mclk_table 630 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->entries[i].mvddInd = mclk_table 632 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c mclk_table->entries[i].clk = mclk_table 636 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c *pp_vega10_mclk_dep_table = mclk_table; mclk_table 2532 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); mclk_table 2535 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int value = mclk_table->dpm_levels[mclk_table->count - 1].value; mclk_table 1488 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct vega20_single_dpm_table *mclk_table = mclk_table 1492 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int value = mclk_table->dpm_levels[mclk_table->count - 1].value; mclk_table 1314 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1315 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1317 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1327 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((dpm_table->mclk_table.count >= 2) mclk_table 1337 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; mclk_table 1338 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1339 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; mclk_table 1659 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (j = 0; j < data->dpm_table.mclk_table.count; j++) { mclk_table 1662 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1704 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 1794 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < data->dpm_table.mclk_table.count; i++) { mclk_table 1797 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->dpm_table.mclk_table.dpm_levels[i].value, mclk_table 1830 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, mclk_table 1238 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1239 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1243 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1261 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint8_t)dpm_table->mclk_table.count; mclk_table 1263 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1265 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c levels[dpm_table->mclk_table.count - 1].DisplayWatermark = mclk_table 1378 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_table.mclk_table.dpm_levels[0].value; mclk_table 1399 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_table.mclk_table.dpm_levels[0].value, mclk_table 1538 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (j = 0; j < data->dpm_table.mclk_table.count; j++) { mclk_table 1541 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1619 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 1361 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1362 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1364 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1382 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; mclk_table 1383 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1385 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; mclk_table 1622 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (j = 0; j < data->dpm_table.mclk_table.count; j++) { mclk_table 1625 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1667 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 1761 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < data->dpm_table.mclk_table.count; i++) { mclk_table 1764 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->dpm_table.mclk_table.dpm_levels[i].value, mclk_table 1798 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count, mclk_table 1139 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1140 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1144 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1146 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c if (i == dpm_table->mclk_table.count - 1) { mclk_table 1163 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint8_t)dpm_table->mclk_table.count; mclk_table 1165 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1262 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c data->dpm_table.mclk_table.dpm_levels[0].value, mclk_table 1371 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { mclk_table 1374 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1377 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); mclk_table 1463 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 1107 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1108 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1113 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1130 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; mclk_table 1131 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1133 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; mclk_table 1498 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (j = 0; j < data->dpm_table.mclk_table.count; j++) { mclk_table 1501 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1545 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 2140 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < data->dpm_table.mclk_table.count; i++) { mclk_table 2143 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_table.mclk_table.dpm_levels[i].value, mclk_table 2180 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->dpm_table.mclk_table.count, mclk_table 1046 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 1047 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), mclk_table 1051 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c dpm_table->mclk_table.dpm_levels[i].value, mclk_table 1064 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint8_t)dpm_table->mclk_table.count; mclk_table 1066 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 1068 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < dpm_table->mclk_table.count; i++) mclk_table 1072 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c levels[dpm_table->mclk_table.count - 1].DisplayWatermark = mclk_table 1177 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c data->dpm_table.mclk_table.dpm_levels[0].value, mclk_table 1297 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { mclk_table 1300 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 1387 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c result = phm_find_boot_level(&(data->dpm_table.mclk_table), mclk_table 2556 drivers/gpu/drm/radeon/ci_dpm.c for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { mclk_table 2559 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.dpm_levels[j].value, mclk_table 3336 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < dpm_table->mclk_table.count; i++) { mclk_table 3337 drivers/gpu/drm/radeon/ci_dpm.c if (dpm_table->mclk_table.dpm_levels[i].value == 0) mclk_table 3340 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->mclk_table.dpm_levels[i].value, mclk_table 3348 drivers/gpu/drm/radeon/ci_dpm.c if ((dpm_table->mclk_table.count >= 2) && mclk_table 3358 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; mclk_table 3360 drivers/gpu/drm/radeon/ci_dpm.c ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); mclk_table 3362 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = mclk_table 3467 drivers/gpu/drm/radeon/ci_dpm.c &pi->dpm_table.mclk_table, mclk_table 3492 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.count = 0; mclk_table 3495 drivers/gpu/drm/radeon/ci_dpm.c (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != mclk_table 3497 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = mclk_table 3499 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = mclk_table 3501 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.count++; mclk_table 3633 drivers/gpu/drm/radeon/ci_dpm.c ret = ci_find_boot_level(&pi->dpm_table.mclk_table, mclk_table 3770 drivers/gpu/drm/radeon/ci_dpm.c &pi->dpm_table.mclk_table, mclk_table 3862 drivers/gpu/drm/radeon/ci_dpm.c struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; mclk_table 3884 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < mclk_table->count; i++) { mclk_table 3885 drivers/gpu/drm/radeon/ci_dpm.c if (mclk == mclk_table->dpm_levels[i].value) mclk_table 3889 drivers/gpu/drm/radeon/ci_dpm.c if (i >= mclk_table->count) mclk_table 3914 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; mclk_table 4181 drivers/gpu/drm/radeon/ci_dpm.c ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); mclk_table 4744 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < pi->dpm_table.mclk_table.count; i++) mclk_table 4746 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.dpm_levels[i].value, mclk_table 4785 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.mclk_table.count, mclk_table 70 drivers/gpu/drm/radeon/ci_dpm.h struct ci_single_dpm_table mclk_table;