mclk_mask        1572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
mclk_mask        1590 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 						 &mclk_mask,
mclk_mask        1595 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
mclk_mask        1292 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 				uint32_t *mclk_mask,
mclk_mask        1309 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	*mclk_mask = 0;
mclk_mask        1316 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
mclk_mask        1323 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*mclk_mask = 0;
mclk_mask        1326 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*mclk_mask = mem_dpm_table->count - 1;
mclk_mask        2728 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
mclk_mask        2746 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		*mclk_mask = golden_dpm_table->mclk_table.count - 1;
mclk_mask        2749 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		*mclk_mask = golden_dpm_table->mclk_table.count - 2;
mclk_mask        2791 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		*mclk_mask = 0;
mclk_mask        2793 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		*mclk_mask = golden_dpm_table->mclk_table.count - 1;
mclk_mask        2807 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint32_t mclk_mask = 0;
mclk_mask        2811 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
mclk_mask        2827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
mclk_mask        2831 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
mclk_mask        4032 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
mclk_mask        4042 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
mclk_mask        4050 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*mclk_mask = 0;
mclk_mask        4054 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
mclk_mask        4142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	uint32_t mclk_mask = 0;
mclk_mask        4146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
mclk_mask        4162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
mclk_mask        4166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
mclk_mask        1583 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
mclk_mask        1591 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	*mclk_mask = 0;
mclk_mask        1598 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
mclk_mask        1605 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*mclk_mask = 0;
mclk_mask        1608 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*mclk_mask = mem_dpm_table->count - 1;
mclk_mask        1638 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	uint32_t mclk_mask = 0;
mclk_mask        1655 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
mclk_mask        1659 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
mclk_mask        2474 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
mclk_mask        2482 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*mclk_mask = 0;
mclk_mask        2489 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
mclk_mask        2496 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*mclk_mask = 0;
mclk_mask        2499 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*mclk_mask = mem_dpm_table->count - 1;
mclk_mask        2673 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
mclk_mask        2692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
mclk_mask        2696 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
mclk_mask         443 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 				      uint32_t *mclk_mask,
mclk_mask         674 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
mclk_mask         675 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
mclk_mask        1215 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 					 uint32_t *mclk_mask,
mclk_mask        1225 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (mclk_mask)
mclk_mask        1226 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*mclk_mask = 0;
mclk_mask        1235 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if(mclk_mask) {
mclk_mask        1239 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*mclk_mask = level_count - 1;
mclk_mask        1989 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			      uint32_t *mclk_mask,
mclk_mask        2005 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	*mclk_mask = 0;
mclk_mask        2012 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
mclk_mask        2019 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*mclk_mask = 0;
mclk_mask        2022 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*mclk_mask = mem_dpm_table->count - 1;