mclk_levels      2771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct SMU7_Discrete_MemoryLevel *mclk_levels =
mclk_levels      2820 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (mclk_levels[i].ActivityLevel !=
mclk_levels      2822 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
mclk_levels      2828 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
mclk_levels      2832 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (mclk_levels[i].UpH != setting->mclk_up_hyst ||
mclk_levels      2833 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				mclk_levels[i].DownH != setting->mclk_down_hyst) {
mclk_levels      2834 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				mclk_levels[i].UpH = setting->mclk_up_hyst;
mclk_levels      2835 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				mclk_levels[i].DownH = setting->mclk_down_hyst;
mclk_levels      2842 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
mclk_levels      2843 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
mclk_levels      2563 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct SMU73_Discrete_MemoryLevel *mclk_levels =
mclk_levels      2612 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			if (mclk_levels[i].ActivityLevel !=
mclk_levels      2614 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
mclk_levels      2620 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
mclk_levels      2624 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
mclk_levels      2625 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
mclk_levels      2626 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				mclk_levels[i].UpHyst = setting->mclk_up_hyst;
mclk_levels      2627 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				mclk_levels[i].DownHyst = setting->mclk_down_hyst;
mclk_levels      2634 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
mclk_levels      2635 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
mclk_levels      2476 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct SMU74_Discrete_MemoryLevel *mclk_levels =
mclk_levels      2525 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			if (mclk_levels[i].ActivityLevel !=
mclk_levels      2527 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
mclk_levels      2533 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
mclk_levels      2537 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
mclk_levels      2538 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
mclk_levels      2539 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				mclk_levels[i].UpHyst = setting->mclk_up_hyst;
mclk_levels      2540 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				mclk_levels[i].DownHyst = setting->mclk_down_hyst;
mclk_levels      2547 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
mclk_levels      2548 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
mclk_levels      3159 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct SMU72_Discrete_MemoryLevel *mclk_levels =
mclk_levels      3208 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			if (mclk_levels[i].ActivityLevel !=
mclk_levels      3210 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
mclk_levels      3216 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
mclk_levels      3220 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
mclk_levels      3221 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
mclk_levels      3222 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mclk_levels[i].UpHyst = setting->mclk_up_hyst;
mclk_levels      3223 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				mclk_levels[i].DownHyst = setting->mclk_down_hyst;
mclk_levels      3230 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
mclk_levels      3231 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));