mclk_edc_wr_enable_threshold 5478 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
mclk_edc_wr_enable_threshold 7388 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	eg_pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 7390 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
mclk_edc_wr_enable_threshold  666 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mclk_edc_wr_enable_threshold;
mclk_edc_wr_enable_threshold 1181 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 1253 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if ((mclk_edc_wr_enable_threshold != 0) &&
mclk_edc_wr_enable_threshold 1254 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				(memory_clock > mclk_edc_wr_enable_threshold)) {
mclk_edc_wr_enable_threshold 1236 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 1301 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if ((mclk_edc_wr_enable_threshold != 0) &&
mclk_edc_wr_enable_threshold 1302 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				(memory_clock > mclk_edc_wr_enable_threshold)) {
mclk_edc_wr_enable_threshold  968 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 1041 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if ((mclk_edc_wr_enable_threshold != 0) &&
mclk_edc_wr_enable_threshold 1042 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(memory_clock > mclk_edc_wr_enable_threshold)) {
mclk_edc_wr_enable_threshold 2617 drivers/gpu/drm/radeon/btc_dpm.c 	eg_pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 2947 drivers/gpu/drm/radeon/ci_dpm.c 		if (pi->mclk_edc_wr_enable_threshold &&
mclk_edc_wr_enable_threshold 2948 drivers/gpu/drm/radeon/ci_dpm.c 		    (memory_clock > pi->mclk_edc_wr_enable_threshold))
mclk_edc_wr_enable_threshold 5773 drivers/gpu/drm/radeon/ci_dpm.c 	pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold  214 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mclk_edc_wr_enable_threshold;
mclk_edc_wr_enable_threshold  711 drivers/gpu/drm/radeon/cypress_dpm.c 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
mclk_edc_wr_enable_threshold 2065 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold   82 drivers/gpu/drm/radeon/cypress_dpm.h 	u32 mclk_edc_wr_enable_threshold;
mclk_edc_wr_enable_threshold 2339 drivers/gpu/drm/radeon/ni_dpm.c 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
mclk_edc_wr_enable_threshold 4132 drivers/gpu/drm/radeon/ni_dpm.c 		eg_pi->mclk_edc_wr_enable_threshold = 55000;
mclk_edc_wr_enable_threshold 4136 drivers/gpu/drm/radeon/ni_dpm.c 		eg_pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 4138 drivers/gpu/drm/radeon/ni_dpm.c 	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
mclk_edc_wr_enable_threshold 5016 drivers/gpu/drm/radeon/si_dpm.c 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
mclk_edc_wr_enable_threshold 6998 drivers/gpu/drm/radeon/si_dpm.c 	eg_pi->mclk_edc_wr_enable_threshold = 40000;
mclk_edc_wr_enable_threshold 7000 drivers/gpu/drm/radeon/si_dpm.c 	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;