mclk_edc_enable_threshold 4926 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 5475 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (pl->mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 7387 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	pi->mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold  575 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mclk_edc_enable_threshold;
mclk_edc_enable_threshold 1182 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold 1248 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if ((mclk_edc_enable_threshold != 0) &&
mclk_edc_enable_threshold 1249 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				(memory_clock > mclk_edc_enable_threshold)) {
mclk_edc_enable_threshold 1237 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint32_t mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold 1296 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if ((mclk_edc_enable_threshold != 0) &&
mclk_edc_enable_threshold 1297 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				(memory_clock > mclk_edc_enable_threshold)) {
mclk_edc_enable_threshold  970 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint32_t mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold 1036 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if ((mclk_edc_enable_threshold != 0) &&
mclk_edc_enable_threshold 1037 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(memory_clock > mclk_edc_enable_threshold)) {
mclk_edc_enable_threshold 2616 drivers/gpu/drm/radeon/btc_dpm.c 	pi->mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold 2943 drivers/gpu/drm/radeon/ci_dpm.c 		if (pi->mclk_edc_enable_threshold &&
mclk_edc_enable_threshold 2944 drivers/gpu/drm/radeon/ci_dpm.c 		    (memory_clock > pi->mclk_edc_enable_threshold))
mclk_edc_enable_threshold 5772 drivers/gpu/drm/radeon/ci_dpm.c 	pi->mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold  213 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mclk_edc_enable_threshold;
mclk_edc_enable_threshold  708 drivers/gpu/drm/radeon/cypress_dpm.c 		if (pl->mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 1317 drivers/gpu/drm/radeon/cypress_dpm.c 		if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 2064 drivers/gpu/drm/radeon/cypress_dpm.c 	pi->mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold 1768 drivers/gpu/drm/radeon/ni_dpm.c 		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 2337 drivers/gpu/drm/radeon/ni_dpm.c 		if (pl->mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 4131 drivers/gpu/drm/radeon/ni_dpm.c 		pi->mclk_edc_enable_threshold = 55000;
mclk_edc_enable_threshold 4135 drivers/gpu/drm/radeon/ni_dpm.c 		pi->mclk_edc_enable_threshold = 40000;
mclk_edc_enable_threshold  647 drivers/gpu/drm/radeon/rv770_dpm.c 			if (pl->mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 1098 drivers/gpu/drm/radeon/rv770_dpm.c 			if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 2381 drivers/gpu/drm/radeon/rv770_dpm.c 	pi->mclk_edc_enable_threshold = 30000;
mclk_edc_enable_threshold  119 drivers/gpu/drm/radeon/rv770_dpm.h 	u32 mclk_edc_enable_threshold;
mclk_edc_enable_threshold 4464 drivers/gpu/drm/radeon/si_dpm.c 		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 5013 drivers/gpu/drm/radeon/si_dpm.c 		if (pl->mclk > pi->mclk_edc_enable_threshold)
mclk_edc_enable_threshold 6997 drivers/gpu/drm/radeon/si_dpm.c 	pi->mclk_edc_enable_threshold = 40000;