mclk_dpm_enable_mask 2632 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
mclk_dpm_enable_mask 2634 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
mclk_dpm_enable_mask 2664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
mclk_dpm_enable_mask 2667 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask 2705 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
mclk_dpm_enable_mask 2707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask 3865 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 4418 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
mclk_dpm_enable_mask  168 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  mclk_dpm_enable_mask;
mclk_dpm_enable_mask  178 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	uint32_t  mclk_dpm_enable_mask;
mclk_dpm_enable_mask  156 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	uint32_t  mclk_dpm_enable_mask;
mclk_dpm_enable_mask  209 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t  mclk_dpm_enable_mask;
mclk_dpm_enable_mask 1338 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
mclk_dpm_enable_mask 1262 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 1383 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
mclk_dpm_enable_mask 1164 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 1131 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
mclk_dpm_enable_mask 1065 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 1070 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
mclk_dpm_enable_mask 3359 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 3833 drivers/gpu/drm/radeon/ci_dpm.c 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
mclk_dpm_enable_mask 3836 drivers/gpu/drm/radeon/ci_dpm.c 								   pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask 3960 drivers/gpu/drm/radeon/ci_dpm.c 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
mclk_dpm_enable_mask 3963 drivers/gpu/drm/radeon/ci_dpm.c 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask 3968 drivers/gpu/drm/radeon/ci_dpm.c 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
mclk_dpm_enable_mask 3971 drivers/gpu/drm/radeon/ci_dpm.c 							  pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask 4180 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
mclk_dpm_enable_mask 4183 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
mclk_dpm_enable_mask 4185 drivers/gpu/drm/radeon/ci_dpm.c 		if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
mclk_dpm_enable_mask 4186 drivers/gpu/drm/radeon/ci_dpm.c 			pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
mclk_dpm_enable_mask 4253 drivers/gpu/drm/radeon/ci_dpm.c 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
mclk_dpm_enable_mask 4255 drivers/gpu/drm/radeon/ci_dpm.c 			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
mclk_dpm_enable_mask 4288 drivers/gpu/drm/radeon/ci_dpm.c 		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
mclk_dpm_enable_mask 4290 drivers/gpu/drm/radeon/ci_dpm.c 							     pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
mclk_dpm_enable_mask  112 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mclk_dpm_enable_mask;