mc_reg_table 5991 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; mc_reg_table 6038 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCRegisters *mc_reg_table) mc_reg_table 6043 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { mc_reg_table 6044 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->mc_reg_table.valid_flag & (1 << j)) { mc_reg_table 6047 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table->address[i].s0 = mc_reg_table 6048 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 6049 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table->address[i].s1 = mc_reg_table 6050 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 6054 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table->last = (u8)i; mc_reg_table 6078 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { mc_reg_table 6079 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) mc_reg_table 6083 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 6086 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 6087 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table_data, si_pi->mc_reg_table.last, mc_reg_table 6088 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 6093 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCRegisters *mc_reg_table) mc_reg_table 6101 drivers/gpu/drm/amd/amdgpu/si_dpm.c &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); mc_reg_table 6122 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 6124 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.last, mc_reg_table 6125 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 6131 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 6133 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.last, mc_reg_table 6134 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 667 drivers/gpu/drm/amd/amdgpu/si_dpm.h struct evergreen_mc_reg_table mc_reg_table; mc_reg_table 822 drivers/gpu/drm/amd/amdgpu/si_dpm.h struct ni_mc_reg_table mc_reg_table; mc_reg_table 962 drivers/gpu/drm/amd/amdgpu/si_dpm.h struct si_mc_reg_table mc_reg_table; mc_reg_table 1722 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_MCRegisters *mc_reg_table) mc_reg_table 1728 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { mc_reg_table 1729 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (smu_data->mc_reg_table.validflag & 1<<j) { mc_reg_table 1732 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mc_reg_table->address[i].s0 = mc_reg_table 1733 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 1734 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mc_reg_table->address[i].s1 = mc_reg_table 1735 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 1740 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mc_reg_table->last = (uint8_t)i; mc_reg_table 1769 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { mc_reg_table 1771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { mc_reg_table 1776 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 1779 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 1780 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c mc_reg_table_data, smu_data->mc_reg_table.last, mc_reg_table 1781 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->mc_reg_table.validflag); mc_reg_table 2678 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table; mc_reg_table 72 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h struct ci_mc_reg_table mc_reg_table; mc_reg_table 1689 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_MCRegisters *mc_reg_table) mc_reg_table 1695 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { mc_reg_table 1696 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (smu_data->mc_reg_table.validflag & 1<<j) { mc_reg_table 1699 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mc_reg_table->address[i].s0 = mc_reg_table 1700 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 1701 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mc_reg_table->address[i].s1 = mc_reg_table 1702 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 1707 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mc_reg_table->last = (uint8_t)i; mc_reg_table 1736 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { mc_reg_table 1738 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { mc_reg_table 1743 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 1746 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 1747 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c mc_reg_table_data, smu_data->mc_reg_table.last, mc_reg_table 1748 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->mc_reg_table.validflag); mc_reg_table 2607 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table; mc_reg_table 67 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h struct iceland_mc_reg_table mc_reg_table; mc_reg_table 2064 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_MCRegisters *mc_reg_table) mc_reg_table 2070 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { mc_reg_table 2071 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if (smu_data->mc_reg_table.validflag & 1<<j) { mc_reg_table 2077 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mc_reg_table->address[i].s0 = mc_reg_table 2078 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 2079 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mc_reg_table->address[i].s1 = mc_reg_table 2080 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 2085 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mc_reg_table->last = (uint8_t)i; mc_reg_table 2115 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { mc_reg_table 2117 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { mc_reg_table 2122 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 2125 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 2126 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mc_reg_table_data, smu_data->mc_reg_table.last, mc_reg_table 2127 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->mc_reg_table.validflag); mc_reg_table 3070 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table; mc_reg_table 71 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h struct tonga_mc_reg_table mc_reg_table; mc_reg_table 2023 drivers/gpu/drm/radeon/btc_dpm.c struct evergreen_mc_reg_table *eg_table = &eg_pi->mc_reg_table; mc_reg_table 4628 drivers/gpu/drm/radeon/ci_dpm.c struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; mc_reg_table 4684 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MCRegisters *mc_reg_table) mc_reg_table 4689 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { mc_reg_table 4690 drivers/gpu/drm/radeon/ci_dpm.c if (pi->mc_reg_table.valid_flag & (1 << j)) { mc_reg_table 4693 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 4694 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 4699 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->last = (u8)i; mc_reg_table 4725 drivers/gpu/drm/radeon/ci_dpm.c for(i = 0; i < pi->mc_reg_table.num_entries; i++) { mc_reg_table 4726 drivers/gpu/drm/radeon/ci_dpm.c if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) mc_reg_table 4730 drivers/gpu/drm/radeon/ci_dpm.c if ((i == pi->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 4733 drivers/gpu/drm/radeon/ci_dpm.c ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 4734 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table_data, pi->mc_reg_table.last, mc_reg_table 4735 drivers/gpu/drm/radeon/ci_dpm.c pi->mc_reg_table.valid_flag); mc_reg_table 4739 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MCRegisters *mc_reg_table) mc_reg_table 4747 drivers/gpu/drm/radeon/ci_dpm.c &mc_reg_table->data[i]); mc_reg_table 228 drivers/gpu/drm/radeon/ci_dpm.h struct ci_mc_reg_table mc_reg_table; mc_reg_table 835 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { mc_reg_table 837 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) mc_reg_table 841 drivers/gpu/drm/radeon/cypress_dpm.c if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 844 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 846 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.last, mc_reg_table 847 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag); mc_reg_table 852 drivers/gpu/drm/radeon/cypress_dpm.c SMC_Evergreen_MCRegisters *mc_reg_table) mc_reg_table 858 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table->data[2]); mc_reg_table 861 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table->data[3]); mc_reg_table 864 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table->data[4]); mc_reg_table 890 drivers/gpu/drm/radeon/cypress_dpm.c SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; mc_reg_table 893 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table); mc_reg_table 899 drivers/gpu/drm/radeon/cypress_dpm.c (u8 *)&mc_reg_table.data[2], mc_reg_table 949 drivers/gpu/drm/radeon/cypress_dpm.c SMC_Evergreen_MCRegisters *mc_reg_table) mc_reg_table 954 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { mc_reg_table 955 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { mc_reg_table 956 drivers/gpu/drm/radeon/cypress_dpm.c mc_reg_table->address[i].s0 = mc_reg_table 957 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 958 drivers/gpu/drm/radeon/cypress_dpm.c mc_reg_table->address[i].s1 = mc_reg_table 959 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 964 drivers/gpu/drm/radeon/cypress_dpm.c mc_reg_table->last = (u8)i; mc_reg_table 972 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; mc_reg_table 973 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; mc_reg_table 976 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; mc_reg_table 977 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; mc_reg_table 980 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; mc_reg_table 981 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; mc_reg_table 984 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; mc_reg_table 985 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; mc_reg_table 988 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; mc_reg_table 989 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; mc_reg_table 992 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; mc_reg_table 993 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; mc_reg_table 996 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; mc_reg_table 997 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; mc_reg_table 1000 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; mc_reg_table 1001 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; mc_reg_table 1004 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_table 1005 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_table 1008 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_table 1009 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_table 1012 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_table 1013 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_table 1016 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; mc_reg_table 1017 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; mc_reg_table 1020 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; mc_reg_table 1021 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; mc_reg_table 1024 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; mc_reg_table 1025 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; mc_reg_table 1028 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.last = (u8)i; mc_reg_table 1037 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) mc_reg_table 1039 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); mc_reg_table 1050 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = mc_reg_table 1054 drivers/gpu/drm/radeon/cypress_dpm.c &eg_pi->mc_reg_table.mc_reg_table_entry[i]); mc_reg_table 1057 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.num_entries = range_table->num_entries; mc_reg_table 1058 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag = 0; mc_reg_table 1060 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) { mc_reg_table 1062 drivers/gpu/drm/radeon/cypress_dpm.c if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != mc_reg_table 1063 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { mc_reg_table 1064 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag |= (1 << i); mc_reg_table 1172 drivers/gpu/drm/radeon/cypress_dpm.c for (i = 0; i < eg_pi->mc_reg_table.last; i++) { mc_reg_table 1173 drivers/gpu/drm/radeon/cypress_dpm.c value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); mc_reg_table 1174 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); mc_reg_table 1670 drivers/gpu/drm/radeon/cypress_dpm.c SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; mc_reg_table 1675 drivers/gpu/drm/radeon/cypress_dpm.c cypress_populate_mc_reg_addresses(rdev, &mc_reg_table); mc_reg_table 1679 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table.data[0]); mc_reg_table 1681 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 1682 drivers/gpu/drm/radeon/cypress_dpm.c &mc_reg_table.data[1], eg_pi->mc_reg_table.last, mc_reg_table 1683 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.valid_flag); mc_reg_table 1685 drivers/gpu/drm/radeon/cypress_dpm.c cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table); mc_reg_table 1688 drivers/gpu/drm/radeon/cypress_dpm.c (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters), mc_reg_table 83 drivers/gpu/drm/radeon/cypress_dpm.h struct evergreen_mc_reg_table mc_reg_table; mc_reg_table 2876 drivers/gpu/drm/radeon/ni_dpm.c struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table; mc_reg_table 2923 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCRegisters *mc_reg_table) mc_reg_table 2928 drivers/gpu/drm/radeon/ni_dpm.c for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) { mc_reg_table 2929 drivers/gpu/drm/radeon/ni_dpm.c if (ni_pi->mc_reg_table.valid_flag & (1 << j)) { mc_reg_table 2932 drivers/gpu/drm/radeon/ni_dpm.c mc_reg_table->address[i].s0 = mc_reg_table 2933 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 2934 drivers/gpu/drm/radeon/ni_dpm.c mc_reg_table->address[i].s1 = mc_reg_table 2935 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 2939 drivers/gpu/drm/radeon/ni_dpm.c mc_reg_table->last = (u8)i; mc_reg_table 2964 drivers/gpu/drm/radeon/ni_dpm.c for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) { mc_reg_table 2965 drivers/gpu/drm/radeon/ni_dpm.c if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) mc_reg_table 2969 drivers/gpu/drm/radeon/ni_dpm.c if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 2972 drivers/gpu/drm/radeon/ni_dpm.c ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 2974 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->mc_reg_table.last, mc_reg_table 2975 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->mc_reg_table.valid_flag); mc_reg_table 2980 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCRegisters *mc_reg_table) mc_reg_table 2988 drivers/gpu/drm/radeon/ni_dpm.c &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); mc_reg_table 2999 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; mc_reg_table 3001 drivers/gpu/drm/radeon/ni_dpm.c memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters)); mc_reg_table 3005 drivers/gpu/drm/radeon/ni_dpm.c ni_populate_mc_reg_addresses(rdev, mc_reg_table); mc_reg_table 3008 drivers/gpu/drm/radeon/ni_dpm.c &mc_reg_table->data[0]); mc_reg_table 3010 drivers/gpu/drm/radeon/ni_dpm.c ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 3011 drivers/gpu/drm/radeon/ni_dpm.c &mc_reg_table->data[1], mc_reg_table 3012 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->mc_reg_table.last, mc_reg_table 3013 drivers/gpu/drm/radeon/ni_dpm.c ni_pi->mc_reg_table.valid_flag); mc_reg_table 3015 drivers/gpu/drm/radeon/ni_dpm.c ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table); mc_reg_table 3018 drivers/gpu/drm/radeon/ni_dpm.c (u8 *)mc_reg_table, mc_reg_table 3030 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; mc_reg_table 3033 drivers/gpu/drm/radeon/ni_dpm.c memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters)); mc_reg_table 3035 drivers/gpu/drm/radeon/ni_dpm.c ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table); mc_reg_table 3041 drivers/gpu/drm/radeon/ni_dpm.c (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], mc_reg_table 182 drivers/gpu/drm/radeon/ni_dpm.h struct ni_mc_reg_table mc_reg_table; mc_reg_table 5537 drivers/gpu/drm/radeon/si_dpm.c struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; mc_reg_table 5584 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCRegisters *mc_reg_table) mc_reg_table 5589 drivers/gpu/drm/radeon/si_dpm.c for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { mc_reg_table 5590 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->mc_reg_table.valid_flag & (1 << j)) { mc_reg_table 5593 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table->address[i].s0 = mc_reg_table 5594 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_table 5595 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table->address[i].s1 = mc_reg_table 5596 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_table 5600 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table->last = (u8)i; mc_reg_table 5624 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { mc_reg_table 5625 drivers/gpu/drm/radeon/si_dpm.c if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) mc_reg_table 5629 drivers/gpu/drm/radeon/si_dpm.c if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) mc_reg_table 5632 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], mc_reg_table 5633 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table_data, si_pi->mc_reg_table.last, mc_reg_table 5634 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 5639 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCRegisters *mc_reg_table) mc_reg_table 5647 drivers/gpu/drm/radeon/si_dpm.c &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); mc_reg_table 5668 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 5670 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.last, mc_reg_table 5671 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 5677 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], mc_reg_table 5679 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.last, mc_reg_table 5680 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); mc_reg_table 155 drivers/gpu/drm/radeon/si_dpm.h struct si_mc_reg_table mc_reg_table;