mc_reg_address 1606 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c reg_table->mc_reg_address[i].s1 = mc_reg_address 1608 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c reg_table->mc_reg_address[i].pre_reg_data = mc_reg_address 1624 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { mc_reg_address 1628 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { mc_reg_address 116 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 5825 drivers/gpu/drm/amd/amdgpu/si_dpm.c switch (table->mc_reg_address[i].s1) { mc_reg_address 5828 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; mc_reg_address 5829 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; mc_reg_address 5839 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; mc_reg_address 5840 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; mc_reg_address 5853 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; mc_reg_address 5854 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; mc_reg_address 5863 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; mc_reg_address 5864 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; mc_reg_address 5955 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? mc_reg_address 5956 drivers/gpu/drm/amd/amdgpu/si_dpm.c address : table->mc_reg_address[i].s1; mc_reg_address 5971 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 6048 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 6050 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 279 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 625 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 933 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 69 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c if ((table->mc_reg_address[i].uc_pre_reg_data & mc_reg_address 74 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c } else if ((table->mc_reg_address[i].uc_pre_reg_data & mc_reg_address 118 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c table->mc_reg_address[i].s1 = mc_reg_address 120 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c table->mc_reg_address[i].uc_pre_reg_data = mc_reg_address 251 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 1733 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 1735 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 2544 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[i].s0 = mc_reg_address 2545 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) mc_reg_address 2546 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ? address : table->mc_reg_address[i].s1; mc_reg_address 2562 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 2591 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c switch (table->mc_reg_address[i].s1) { mc_reg_address 2595 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; mc_reg_address 2596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; mc_reg_address 2607 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; mc_reg_address 2608 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; mc_reg_address 2622 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; mc_reg_address 2623 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; mc_reg_address 2635 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; mc_reg_address 2636 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; mc_reg_address 58 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 1700 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 1702 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 2473 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[i].s0 = mc_reg_address 2474 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) mc_reg_address 2475 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ? address : table->mc_reg_address[i].s1; mc_reg_address 2491 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 2520 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c switch (table->mc_reg_address[i].s1) { mc_reg_address 2524 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; mc_reg_address 2525 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; mc_reg_address 2536 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; mc_reg_address 2537 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; mc_reg_address 2552 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; mc_reg_address 2553 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; mc_reg_address 2565 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; mc_reg_address 2566 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; mc_reg_address 57 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 2078 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 2080 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 2934 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[i].s0 = mc_reg_address 2935 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, mc_reg_address 2938 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[i].s1; mc_reg_address 2954 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 2983 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c switch (table->mc_reg_address[i].s1) { mc_reg_address 2988 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; mc_reg_address 2989 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; mc_reg_address 3000 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; mc_reg_address 3001 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; mc_reg_address 3015 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; mc_reg_address 3016 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; mc_reg_address 3027 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; mc_reg_address 3028 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; mc_reg_address 59 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 1925 drivers/gpu/drm/radeon/btc_dpm.c switch (table->mc_reg_address[i].s1) { mc_reg_address 1928 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_address 1929 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_address 1941 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_address 1942 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_address 1957 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_address 1958 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_address 1985 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_address[i].s0 = mc_reg_address 1986 drivers/gpu/drm/radeon/btc_dpm.c btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? mc_reg_address 1987 drivers/gpu/drm/radeon/btc_dpm.c address : table->mc_reg_address[i].s1; mc_reg_address 2003 drivers/gpu/drm/radeon/btc_dpm.c eg_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 4346 drivers/gpu/drm/radeon/ci_dpm.c switch(table->mc_reg_address[i].s1 << 2) { mc_reg_address 4349 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_address 4350 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_address 4360 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_address 4361 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_address 4373 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; mc_reg_address 4374 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; mc_reg_address 4386 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_address 4387 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_address 4501 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_address[i].s0 = mc_reg_address 4502 drivers/gpu/drm/radeon/ci_dpm.c ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? mc_reg_address 4503 drivers/gpu/drm/radeon/ci_dpm.c address : table->mc_reg_address[i].s1; mc_reg_address 4518 drivers/gpu/drm/radeon/ci_dpm.c ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 4550 drivers/gpu/drm/radeon/ci_dpm.c switch(table->mc_reg_address[i].s1 >> 2) { mc_reg_address 4693 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 4694 drivers/gpu/drm/radeon/ci_dpm.c mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 87 drivers/gpu/drm/radeon/ci_dpm.h SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 957 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 959 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 972 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; mc_reg_address 973 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; mc_reg_address 976 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; mc_reg_address 977 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; mc_reg_address 980 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; mc_reg_address 981 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; mc_reg_address 984 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; mc_reg_address 985 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; mc_reg_address 988 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; mc_reg_address 989 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; mc_reg_address 992 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; mc_reg_address 993 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; mc_reg_address 996 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; mc_reg_address 997 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; mc_reg_address 1000 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; mc_reg_address 1001 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; mc_reg_address 1004 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_address 1005 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_address 1008 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_address 1009 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_address 1012 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_address 1013 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_address 1016 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; mc_reg_address 1017 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; mc_reg_address 1020 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; mc_reg_address 1021 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; mc_reg_address 1024 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; mc_reg_address 1025 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; mc_reg_address 1039 drivers/gpu/drm/radeon/cypress_dpm.c RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); mc_reg_address 1173 drivers/gpu/drm/radeon/cypress_dpm.c value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); mc_reg_address 1174 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); mc_reg_address 39 drivers/gpu/drm/radeon/cypress_dpm.h SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 2717 drivers/gpu/drm/radeon/ni_dpm.c switch (table->mc_reg_address[i].s1) { mc_reg_address 2722 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_address 2723 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_address 2733 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_address 2734 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_address 2748 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_address 2749 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_address 2840 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_address[i].s0 = mc_reg_address 2841 drivers/gpu/drm/radeon/ni_dpm.c ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? mc_reg_address 2842 drivers/gpu/drm/radeon/ni_dpm.c address : table->mc_reg_address[i].s1; mc_reg_address 2856 drivers/gpu/drm/radeon/ni_dpm.c ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 2933 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 2935 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 57 drivers/gpu/drm/radeon/ni_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 4024 drivers/gpu/drm/radeon/radeon_atombios.c reg_table->mc_reg_address[i].s1 = mc_reg_address 4026 drivers/gpu/drm/radeon/radeon_atombios.c reg_table->mc_reg_address[i].pre_reg_data = mc_reg_address 4042 drivers/gpu/drm/radeon/radeon_atombios.c if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { mc_reg_address 4046 drivers/gpu/drm/radeon/radeon_atombios.c } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { mc_reg_address 668 drivers/gpu/drm/radeon/radeon_mode.h struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; mc_reg_address 5366 drivers/gpu/drm/radeon/si_dpm.c switch (table->mc_reg_address[i].s1 << 2) { mc_reg_address 5369 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; mc_reg_address 5370 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; mc_reg_address 5380 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; mc_reg_address 5381 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; mc_reg_address 5394 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; mc_reg_address 5395 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; mc_reg_address 5406 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; mc_reg_address 5407 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; mc_reg_address 5501 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? mc_reg_address 5502 drivers/gpu/drm/radeon/si_dpm.c address : table->mc_reg_address[i].s1; mc_reg_address 5517 drivers/gpu/drm/radeon/si_dpm.c si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; mc_reg_address 5594 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); mc_reg_address 5596 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); mc_reg_address 117 drivers/gpu/drm/radeon/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];