mc_err_base        49 drivers/edac/highbank_mc_edac.c 	void __iomem *mc_err_base;
mc_err_base        63 drivers/edac/highbank_mc_edac.c 		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
mc_err_base        71 drivers/edac/highbank_mc_edac.c 		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
mc_err_base        73 drivers/edac/highbank_mc_edac.c 		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
mc_err_base        91 drivers/edac/highbank_mc_edac.c 	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
mc_err_base        94 drivers/edac/highbank_mc_edac.c 	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
mc_err_base       202 drivers/edac/highbank_mc_edac.c 	drvdata->mc_err_base = base + settings->err_offset;
mc_err_base       205 drivers/edac/highbank_mc_edac.c 	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;