maxver             47 drivers/gpu/drm/nouveau/include/nvif/ioctl.h 		__s16 maxver;
maxver             10 drivers/gpu/drm/nouveau/include/nvif/object.h 	int maxver;
maxver             91 drivers/gpu/drm/nouveau/include/nvif/object.h 				    mclass[i].version <= sclass[j].maxver) {   \
maxver             10 drivers/gpu/drm/nouveau/include/nvkm/core/oclass.h 	int maxver;
maxver             91 drivers/gpu/drm/nouveau/nvif/object.c 			(*psclass)[i].maxver = args->sclass.oclass[i].maxver;
maxver             67 drivers/gpu/drm/nouveau/nvkm/core/client.c 	.maxver = 0,
maxver             71 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c 				args->v0.oclass[i].maxver = oclass.base.maxver;
maxver            210 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	.base.maxver = -1,
maxver            454 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c 	.maxver = 0,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c 	.base.maxver = -1,
maxver             53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c 	.base.maxver = -1,
maxver             50 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c 	.base.maxver = -1,
maxver             96 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c 	.base.maxver = -1,
maxver            359 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c 	.base.maxver = -1,
maxver             50 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c 	.base.maxver = -1,
maxver             92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c 	.base.maxver = 0,
maxver            224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 	.base.maxver = 0,
maxver             95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 	.base.maxver = 0,
maxver             96 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 	.base.maxver = 0,
maxver            244 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 	.base.maxver = 0,
maxver             90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c 	.base.maxver = 0,
maxver             93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c 	.base.maxver = 0,
maxver            299 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c 	.base.maxver = 0,
maxver             91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c 	.base.maxver = 0,
maxver            619 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 		oclass->base.maxver = 0;
maxver            686 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c 	.base.maxver = -1,
maxver            376 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c 	const bool more = oclass->base.maxver >= 0;
maxver             71 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h 	int (*load)(const struct nvkm_secboot *, int maxver,
maxver             93 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, int maxver,
maxver            149 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c acr_ls_ucode_load_fecs(const struct nvkm_secboot *sb, int maxver,
maxver            152 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	return ls_ucode_img_load_gr(&sb->subdev, maxver, img, "fecs");
maxver            156 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c acr_ls_ucode_load_gpccs(const struct nvkm_secboot *sb, int maxver,
maxver            159 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c 	return ls_ucode_img_load_gr(&sb->subdev, maxver, img, "gpccs");
maxver             42 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c 			   int maxver, struct ls_ucode_img *img)
maxver             49 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c 	ver = nvkm_firmware_get_version(subdev, f, 0, maxver, &image);
maxver            102 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c acr_ls_ucode_load_pmu(const struct nvkm_secboot *sb, int maxver,
maxver            108 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c 	ret = acr_ls_ucode_load_msgqueue(&sb->subdev, "pmu", maxver, img);
maxver            140 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c acr_ls_ucode_load_sec2(const struct nvkm_secboot *sb, int maxver,
maxver            146 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c 	ver = acr_ls_ucode_load_msgqueue(&sb->subdev, "sec2", maxver, img);
maxver             93 drivers/net/ethernet/intel/i40e/i40e_dcb.h 	u8 maxver;
maxver             96 drivers/net/ethernet/intel/ice/ice_dcb.h 	u8 maxver;