max_slice_width   804 drivers/gpu/drm/amd/display/dc/dc_types.h 	int32_t max_slice_width;
max_slice_width   146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
max_slice_width   248 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_common_caps->max_slice_width = min(dsc_sink_caps->max_slice_width, dsc_enc_caps->max_slice_width);
max_slice_width   249 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (!dsc_common_caps->max_slice_width)
max_slice_width   624 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = (dsc_common_caps.max_slice_width > 0);
max_slice_width   628 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	min_slices_h = pic_width / dsc_common_caps.max_slice_width;
max_slice_width   629 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (pic_width % dsc_common_caps.max_slice_width)
max_slice_width   677 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
max_slice_width   759 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_sink_caps->max_slice_width = dpcd_dsc_basic_data[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 320;
max_slice_width    80 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	int32_t max_slice_width;
max_slice_width   554 drivers/gpu/drm/i915/display/intel_dp.c 	int max_slice_width;
max_slice_width   563 drivers/gpu/drm/i915/display/intel_dp.c 	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
max_slice_width   564 drivers/gpu/drm/i915/display/intel_dp.c 	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
max_slice_width   566 drivers/gpu/drm/i915/display/intel_dp.c 			      max_slice_width);
max_slice_width   572 drivers/gpu/drm/i915/display/intel_dp.c 					     max_slice_width));