max_r_for_parent  186 drivers/clk/analogbits/wrpll-cln28hpc.c 	u8 max_r_for_parent;
max_r_for_parent  192 drivers/clk/analogbits/wrpll-cln28hpc.c 	max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
max_r_for_parent  193 drivers/clk/analogbits/wrpll-cln28hpc.c 	c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);