max_post_divider 256 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_post_divider, max_post_divider 271 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c post_divider = max_post_divider; max_post_divider 298 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t max_post_divider; max_post_divider 311 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_post_divider = pll_settings->pix_clk_post_divider; max_post_divider 324 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; max_post_divider 325 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (max_post_divider * pll_settings->adjusted_pix_clk_100hz max_post_divider 327 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_post_divider = calc_pll_cs->max_vco_khz * 10 / max_post_divider 363 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (min_post_divider > max_post_divider) { max_post_divider 386 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_post_divider,