max_pll_ref_divider 350 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c < calc_pll_cs->max_pll_ref_divider) max_pll_ref_divider 353 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c : calc_pll_cs->max_pll_ref_divider; max_pll_ref_divider 1275 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs->max_pll_ref_divider = max_pll_ref_divider 1276 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c init_data->max_pll_ref_divider; max_pll_ref_divider 1344 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; max_pll_ref_divider 1363 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; max_pll_ref_divider 125 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pll_ref_divider; max_pll_ref_divider 146 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t max_pll_ref_divider;