MPCC_TOP_SEL 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); MPCC_TOP_SEL 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c MPCC_TOP_SEL, &top_sel); MPCC_TOP_SEL 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); MPCC_TOP_SEL 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); MPCC_TOP_SEL 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); MPCC_TOP_SEL 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); MPCC_TOP_SEL 374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); MPCC_TOP_SEL 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); MPCC_TOP_SEL 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); MPCC_TOP_SEL 439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); MPCC_TOP_SEL 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_TOP_SEL, MPCC, inst),\ MPCC_TOP_SEL 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_TOP_SEL[MAX_MPCC]; \ MPCC_TOP_SEL 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ MPCC_TOP_SEL 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h type MPCC_TOP_SEL;\ MPCC_TOP_SEL 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c MPCC_TOP_SEL, &top_sel);