MPCC_STATUS       101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_WAIT(MPCC_STATUS[id],
MPCC_STATUS       135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_STATUS[mpcc_id],  MPCC_IDLE,   &idle);
MPCC_STATUS       151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_GET_2(MPCC_STATUS[mpcc_id],
MPCC_STATUS       445 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
MPCC_STATUS        37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SRII(MPCC_STATUS, MPCC, inst),\
MPCC_STATUS        52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MPCC_STATUS[MAX_MPCC]; \
MPCC_STATUS       436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled);
MPCC_STATUS       440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_WAIT(MPCC_STATUS[id],
MPCC_STATUS       453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_GET_3(MPCC_STATUS[mpcc_id],