MPCC_SM_CONTROL    88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
MPCC_SM_CONTROL    43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SRII(MPCC_SM_CONTROL, MPCC, inst)
MPCC_SM_CONTROL    57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \