MPCC_OPP_ID       134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_OPP_ID[mpcc_id],  MPCC_OPP_ID, &opp_id);
MPCC_OPP_ID       217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
MPCC_OPP_ID       313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
MPCC_OPP_ID       323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
MPCC_OPP_ID       356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
MPCC_OPP_ID       372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
MPCC_OPP_ID       376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
MPCC_OPP_ID       402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_GET(MPCC_OPP_ID[mpcc_id],  MPCC_OPP_ID,  &opp_id);
MPCC_OPP_ID       418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					REG_GET(MPCC_OPP_ID[bot_mpcc_id],  MPCC_OPP_ID,  &opp_id);
MPCC_OPP_ID       438 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
MPCC_OPP_ID        38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SRII(MPCC_OPP_ID, MPCC, inst),\
MPCC_OPP_ID        53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MPCC_OPP_ID[MAX_MPCC]; \
MPCC_OPP_ID        71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
MPCC_OPP_ID        94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	type MPCC_OPP_ID;\