MPCC_OGAM_RAMB_END_CNTL1_R  304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
MPCC_OGAM_RAMB_END_CNTL1_R   62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
MPCC_OGAM_RAMB_END_CNTL1_R  112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \